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fix(intel): update DDR range checking for Agilex5

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Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.

Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This commit is contained in:
Sieu Mun Tang 2023-09-25 22:30:34 +08:00 • committed by Jit Loon Lim
parent 93823fb6ec
commit f4aaa9fd6e
1 changed files with 4 additions and 1 deletions
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5
plat/intel/soc/common/socfpga_sip_svc.c
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@ -280,6 +280,9 @@ static bool is_fpga_config_buffer_full(void)
bool is_address_in_ddr_range(uint64_t addr, uint64_t size) bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
{ {
uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE;
uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size;
if (!addr && !size) { if (!addr && !size) {
return true; return true;
} }
@ -289,7 +292,7 @@ bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
if (addr < BL31_LIMIT) { if (addr < BL31_LIMIT) {
return false; return false;
} }
if (addr + size > DRAM_BASE + DRAM_SIZE) { if (dram_region_end > dram_max_sz) {
return false; return false;
} }