From f4aaa9fd6e6b4edd03976680b94e1c24aa582a68 Mon Sep 17 00:00:00 2001 From: Sieu Mun Tang Date: Mon, 25 Sep 2023 22:30:34 +0800 Subject: [PATCH] fix(intel): update DDR range checking for Agilex5 Update DDR range checking for Agilex when total max size of DRAM_BASE and DRAM_SIZE overflow unsigned 64bit. Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2 Signed-off-by: Sieu Mun Tang Signed-off-by: Jit Loon Lim --- plat/intel/soc/common/socfpga_sip_svc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index c6530cf31..314a7d778 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -280,6 +280,9 @@ static bool is_fpga_config_buffer_full(void) bool is_address_in_ddr_range(uint64_t addr, uint64_t size) { + uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; + uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; + if (!addr && !size) { return true; } @@ -289,7 +292,7 @@ bool is_address_in_ddr_range(uint64_t addr, uint64_t size) if (addr < BL31_LIMIT) { return false; } - if (addr + size > DRAM_BASE + DRAM_SIZE) { + if (dram_region_end > dram_max_sz) { return false; }