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Merge changes from topic "ar/cvereorder" into integration

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* changes:
  chore(cpus): fix cve order in Neoverse-V2
  chore(cpus): rearrange the errata and cve in order in Cortex-A710
This commit is contained in:
Bipin Ravi 2025-03-21 17:12:25 +01:00 • committed by TrustedFirmware Code Review
commit eeb16181f5
2 changed files with 16 additions and 16 deletions

18
lib/cpus/aarch64/cortex_a710.S
View file

@ -31,13 +31,6 @@
cpu_reset_prologue cortex_a710
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
workaround_reset_end cortex_a710, CVE(2024, 5660)
check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
@ -213,6 +206,10 @@ workaround_reset_end cortex_a710, ERRATUM(2778471)
check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1)
add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
@ -225,9 +222,12 @@ workaround_reset_end cortex_a710, CVE(2022, 23960)
check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
workaround_reset_end cortex_a710, CVE(2024, 5660)
check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down

14
lib/cpus/aarch64/neoverse_v2.S
View file

@ -24,13 +24,6 @@
cpu_reset_prologue neoverse_v2
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46)
workaround_reset_end neoverse_v2, CVE(2024, 5660)
check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2)
workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
@ -95,6 +88,13 @@ workaround_reset_end neoverse_v2, CVE(2022,23960)
check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46)
workaround_reset_end neoverse_v2, CVE(2024, 5660)
check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2)
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
#endif /* WORKAROUND_CVE_2022_23960 */