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Merge changes from topic "ar/cvereorder" into integration
* changes: chore(cpus): fix cve order in Neoverse-V2 chore(cpus): rearrange the errata and cve in order in Cortex-A710
This commit is contained in:
commit
eeb16181f5
2 changed files with 16 additions and 16 deletions
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@ -31,13 +31,6 @@
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cpu_reset_prologue cortex_a710
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cpu_reset_prologue cortex_a710
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a710, CVE(2024, 5660)
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check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
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workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
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workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
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ldr x0,=0x6
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ldr x0,=0x6
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msr S3_6_c15_c8_0,x0
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msr S3_6_c15_c8_0,x0
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@ -213,6 +206,10 @@ workaround_reset_end cortex_a710, ERRATUM(2778471)
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check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1)
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check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1)
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add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
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check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
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workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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#if IMAGE_BL31
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/*
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/*
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@ -225,9 +222,12 @@ workaround_reset_end cortex_a710, CVE(2022, 23960)
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check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_a710, CVE(2024, 5660)
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check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
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check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
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/* ----------------------------------------------------
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* HW will do the cache maintenance while powering down
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@ -24,13 +24,6 @@
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cpu_reset_prologue neoverse_v2
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cpu_reset_prologue neoverse_v2
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46)
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workaround_reset_end neoverse_v2, CVE(2024, 5660)
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check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2)
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workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
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workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
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sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
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sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
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NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
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NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
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@ -95,6 +88,13 @@ workaround_reset_end neoverse_v2, CVE(2022,23960)
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check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46)
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workaround_reset_end neoverse_v2, CVE(2024, 5660)
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check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2)
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#if WORKAROUND_CVE_2022_23960
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
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#endif /* WORKAROUND_CVE_2022_23960 */
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#endif /* WORKAROUND_CVE_2022_23960 */
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