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fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
[IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.41. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168
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2 changed files with 9 additions and 3 deletions
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@ -4147,7 +4147,13 @@ int32_t rcar_dram_init(void)
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}
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/* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
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data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
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data_l = mmio_read_32(THS1_THCTR);
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if (data_l & 0x00000040U) {
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data_l = data_l & 0xFFFFFFBEU;
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} else {
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data_l = data_l | BIT(1);
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}
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mmio_write_32(THS1_THCTR, data_l);
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/* Judge product and cut */
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@ -1,11 +1,11 @@
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/*
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* Copyright (c) 2015-2020, Renesas Electronics Corporation.
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* Copyright (c) 2015-2021, Renesas Electronics Corporation.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define RCAR_DDR_VERSION "rev.0.40"
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#define RCAR_DDR_VERSION "rev.0.41"
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#define DRAM_CH_CNT 0x04
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#define SLICE_CNT 0x04
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#define CS_CNT 0x02
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