From ec767c1b99675fbb50ef1b2fdb2d38e881e4789d Mon Sep 17 00:00:00 2001 From: Chiaki Fujii Date: Fri, 30 Oct 2020 10:45:18 +0900 Subject: [PATCH] fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N [IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.41. Signed-off-by: Chiaki Fujii Signed-off-by: Yoshifumi Hosoya Change-Id: Idd2fbea621365d84b566748b5b7d7fb2f0d08168 --- drivers/renesas/common/ddr/ddr_b/boot_init_dram.c | 8 +++++++- drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c index aa3bc245b..8d002deca 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c @@ -4147,7 +4147,13 @@ int32_t rcar_dram_init(void) } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ - data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; + data_l = mmio_read_32(THS1_THCTR); + if (data_l & 0x00000040U) { + data_l = data_l & 0xFFFFFFBEU; + } else { + data_l = data_l | BIT(1); + } + mmio_write_32(THS1_THCTR, data_l); /* Judge product and cut */ diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h index 56363eb99..3cb19752c 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_DDR_VERSION "rev.0.40" +#define RCAR_DDR_VERSION "rev.0.41" #define DRAM_CH_CNT 0x04 #define SLICE_CNT 0x04 #define CS_CNT 0x02