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Merge changes I65b9e341,I7f3c42cb,I1bb1771d into integration

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* changes:
  feat(mt8196): add reset and poweroff function for PSCI call
  feat(mt8196): refactor LPM header include paths to use lpm_v2
  refactor(mediatek): update API calls to MTK GIC v3 driver
This commit is contained in:
Govindraj Raja 2025-02-05 21:19:04 +01:00 • committed by TrustedFirmware Code Review
commit e6cbdb00b7
8 changed files with 36 additions and 15 deletions
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6
plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_cpu_pm.c
View file

@ -14,7 +14,7 @@
#include <lib/mtk_init/mtk_init.h>
#include <lib/pm/mtk_pm.h>
#include <lpm/mt_lp_rm.h>
#include <lpm_v2/mt_lp_rm.h>
#include "mt_cpu_pm.h"
#include "mt_cpu_pm_cpc.h"
#include "mt_cpu_pm_mbox.h"
@ -773,11 +773,13 @@ static int cpupm_pwr_state_valid(unsigned int afflv, unsigned int state)
static int cpupm_invoke(unsigned int func_id, void *priv)
{
int ret = MTK_CPUPM_E_OK;
#ifdef CPU_PM_SUSPEND_NOTIFY
int i, reverse = 0;
struct cpupm_invoke_data *save_status = (struct cpupm_invoke_data *) priv;
unsigned int cpu_status;
#endif
struct cpupm_pwr_req *req = (struct cpupm_pwr_req *)priv;
unsigned int pwr_req = req->req;
unsigned int cpu_status;
switch (func_id) {
#ifdef CPU_PM_SUSPEND_NOTIFY

6
plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_cpu_pm_smc.h
View file

@ -7,9 +7,9 @@
#ifndef MT_CPU_PM_SMC_H
#define MT_CPU_PM_SMC_H
#include <lpm/mt_lp_rm.h>
#include <lpm/mt_lpm_dispatch.h>
#include <lpm/mt_lpm_smc.h>
#include <lpm_v2/mt_lp_rm.h>
#include <lpm_v2/mt_lpm_dispatch.h>
#include <lpm_v2/mt_lpm_smc.h>
void cpupm_smc_init(void);

2
plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
View file

@ -12,7 +12,7 @@
#include <platform_def.h>
#include <lib/pm/mtk_pm.h>
#include <lpm/mt_lp_rm.h>
#include <lpm_v2/mt_lp_rm.h>
#include "mt_cpu_pm.h"
#include "mt_lp_irqremain.h"

2
plat/mediatek/drivers/cpu_pm/cpcv5_4/rules.mk
View file

@ -29,8 +29,6 @@ $(eval $(call add_defined_option,CPU_PM_DOMAIN_CORE_ONLY))
$(eval $(call add_defined_option,CPU_PM_CORE_ARCH64_ONLY))
$(eval $(call add_defined_option,CPU_PM_TINYSYS_SUPPORT))
$(eval $(call add_defined_option,CPU_PM_SUSPEND_NOTIFY))
$(eval $(call add_defined_option,CPU_PM_PWR_REQ))
$(eval $(call add_defined_option,CPU_PM_PWR_REQ_DEBUG))

18
plat/mediatek/lib/pm/armv9_0/pwr_ctrl.c
View file

@ -16,6 +16,7 @@
#include <drivers/console.h>
#include <lib/psci/psci.h>
#include <lib/utils.h>
#include <mt_gic_v3.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@ -108,6 +109,9 @@ static inline unsigned int get_pwr_afflv(const psci_power_state_t *state)
static void mcusys_pwr_on_common(const struct mtk_cpupm_pwrstate *state)
{
mt_gic_distif_restore();
mt_gic_rdistif_restore();
if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_RESUME_MCUSYS))
imtk_cpu_pwr.ops->mcusys_resume(state);
}
@ -121,6 +125,9 @@ static void mcusys_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state)
if (IS_CPUIDLE_FN_ENABLE(MTK_CPUPM_FN_SUSPEND_MCUSYS))
imtk_cpu_pwr.ops->mcusys_suspend(state);
mt_gic_rdistif_save();
/* save gic context after cirq enable */
mt_gic_distif_save();
}
static void cluster_pwr_on_common(const struct mtk_cpupm_pwrstate *state)
@ -140,8 +147,7 @@ static void cpu_pwr_on_common(const struct mtk_cpupm_pwrstate *state,
{
coordinate_cluster_pwron();
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
mt_gic_cpuif_enable();
}
static void cpu_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state,
@ -149,6 +155,8 @@ static void cpu_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state,
{
if (pstate & MT_CPUPM_PWR_DOMAIN_PERCORE_DSU)
coordinate_cluster_pwroff();
mt_gic_cpuif_disable();
}
static void cpu_pwr_resume(const struct mtk_cpupm_pwrstate *state,
@ -217,6 +225,8 @@ static void power_domain_on_finish(const psci_power_state_t *state)
},
};
mt_gic_pcpu_init();
cpu_pwr_on(&pm_state, pstate);
nb.cpuid = pm_state.info.cpuid;
@ -243,7 +253,7 @@ static void power_domain_off(const psci_power_state_t *state)
cpu_pwr_off(&pm_state, pstate);
gicv3_rdistif_off(plat_my_core_pos());
mt_gic_redistif_off();
nb.cpuid = pm_state.info.cpuid;
nb.pwr_domain = pstate;
@ -278,8 +288,6 @@ static void power_domain_suspend(const psci_power_state_t *state)
if (pstate & MT_CPUPM_PWR_DOMAIN_MCUSYS)
mcusys_pwr_dwn_common(&pm_state);
gicv3_rdistif_off(plat_my_core_pos());
nb.cpuid = pm_state.info.cpuid;
nb.pwr_domain = pstate;
MT_CPUPM_EVENT_PWR_OFF(&nb);

14
plat/mediatek/lib/system_reset/reset_cros.c
View file

@ -1,18 +1,25 @@
/*
* Copyright (c) 2022, MediaTek Inc. All rights reserved.
* Copyright (c) 2022-2025, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <drivers/gpio.h>
#if CONFIG_MTK_PMIC_SHUTDOWN_CFG
#include <drivers/pmic/pmic_psc.h>
#endif
#include <lib/mtk_init/mtk_init.h>
#include <lib/pm/mtk_pm.h>
#include <plat_params.h>
#if !CONFIG_MTK_PMIC_SHUTDOWN_CFG
#include <pmic.h>
#include <rtc.h>
#endif
static void __dead2 mtk_system_reset_cros(void)
{
@ -31,8 +38,13 @@ static void __dead2 mtk_system_off_cros(void)
{
INFO("MTK System Off\n");
#if CONFIG_MTK_PMIC_SHUTDOWN_CFG
platform_power_hold(false);
mdelay(1000);
#else
rtc_power_off_sequence();
pmic_power_off();
#endif
wfi();
ERROR("MTK System Off: operation not handled.\n");

2
plat/mediatek/mt8196/include/platform_def.h
View file

@ -87,7 +87,7 @@
* GPIO related constants
******************************************************************************/
#define GPIO_BASE (IO_PHYS + 0x0002D000)
#define RGU_BASE (IO_PHYS + 0x0C00B000)
#define RGU_BASE (IO_PHYS + 0x0C010000)
#define DRM_BASE (IO_PHYS + 0x0000D000)
#define IOCFG_RT_BASE (IO_PHYS + 0x02000000)
#define IOCFG_RM1_BASE (IO_PHYS + 0x02020000)

1
plat/mediatek/mt8196/platform.mk
View file

@ -41,6 +41,7 @@ MODULES-y += $(MTK_PLAT)/common
MODULES-y += $(MTK_PLAT)/common/lpm_v2
MODULES-y += $(MTK_PLAT)/lib/mtk_init
MODULES-y += $(MTK_PLAT)/lib/pm
MODULES-y += $(MTK_PLAT)/lib/system_reset
MODULES-y += $(MTK_PLAT)/drivers/apusys
MODULES-y += $(MTK_PLAT)/drivers/cirq
MODULES-y += $(MTK_PLAT)/drivers/dp