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Merge changes from topic "allwinner_t507" into integration

Browse source 
* changes:
  feat(allwinner): add support for Allwinner T507 SoC
  feat(allwinner): add function to detect H616 die variant
  feat(allwinner): add extra CPU control registers
  refactor(allwinner): consolidate sunxi_cfg.h files
This commit is contained in:
Madhukar Pappireddy 2023-05-04 15:19:50 +02:00 • committed by TrustedFirmware Code Review
commit e603983d37
13 changed files with 187 additions and 129 deletions
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2
docs/plat/allwinner.rst
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@ -23,6 +23,8 @@ There is one build target per supported SoC:
+------+-------------------+
| H313 | sun50i_h616 |
+------+-------------------+
| T507 | sun50i_h616 |
+------+-------------------+
| R329 | sun50i_r329 |
+------+-------------------+

43
plat/allwinner/common/include/sunxi_cpucfg_ncat.h Normal file
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@ -0,0 +1,43 @@
/*
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SUNXI_CPUCFG_H
#define SUNXI_CPUCFG_H
#include <sunxi_mmap.h>
/* c = cluster, n = core */
#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024)
/* The T507 datasheet does not mention this register. */
#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0)
#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
#define SUNXI_C0_CPU_CTRL_REG(n) (SUNXI_CPUCFG_BASE + 0x0060 + (n) * 4)
#define SUNXI_CPU_CTRL_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x20 + (n) * 4)
#define SUNXI_ALT_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x40 + (n) * 8)
#define SUNXI_ALT_RVBAR_HI_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x44 + (n) * 8)
#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
(c) * 0x10 + (n) * 4)
#define SUNXI_CPU_UNK_REG(n) (SUNXI_R_CPUCFG_BASE + 0x0070 + (n) * 4)
#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 24
#endif /* SUNXI_CPUCFG_H */

36
plat/allwinner/common/include/sunxi_cpucfg_ncat2.h Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (c) 2021 Sipeed
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SUNXI_CPUCFG_H
#define SUNXI_CPUCFG_H
#include <sunxi_mmap.h>
/* c = cluster, n = core */
#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010)
#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014)
#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024)
#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0)
#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000)
#define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000)
#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
(c) * 0x10 + (n) * 4)
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 4
static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
{
return true;
}
#endif /* SUNXI_CPUCFG_H */

1
plat/allwinner/common/include/sunxi_def.h
View file

@ -20,6 +20,7 @@
#define SUNXI_SOC_H616 0x1823
#define SUNXI_SOC_R329 0x1851
#define SUNXI_VER_BITS_MASK 0xffU
#define JEDEC_ALLWINNER_BKID 9U
#define JEDEC_ALLWINNER_MFID 0x9eU

2
plat/allwinner/common/sunxi_common.c
View file

@ -183,5 +183,5 @@ int32_t plat_get_soc_revision(void)
{
uint32_t reg = mmio_read_32(SRAM_VER_REG);
return reg & GENMASK_32(7, 0);
return reg & SUNXI_VER_BITS_MASK;
}

95
plat/allwinner/common/sunxi_cpu_ops.c
View file

@ -19,6 +19,12 @@
#include <sunxi_mmap.h>
#include <sunxi_private.h>
#ifndef SUNXI_C0_CPU_CTRL_REG
#define SUNXI_C0_CPU_CTRL_REG(n) 0
#define SUNXI_CPU_UNK_REG(n) 0
#define SUNXI_CPU_CTRL_REG(n) 0
#endif
static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
{
if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
@ -53,15 +59,30 @@ static void sunxi_cpu_off(u_register_t mpidr)
VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
/* Deassert DBGPWRDUP */
mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
/* Activate the core output clamps, but not for core 0. */
if (core != 0)
mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
/* Assert CPU power-on reset */
mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Remove power from the CPU */
sunxi_cpu_disable_power(cluster, core);
if (sunxi_cpucfg_has_per_cluster_regs()) {
/* Deassert DBGPWRDUP */
mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
/* Activate the core output clamps, but not for core 0. */
if (core != 0) {
mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
BIT(core));
}
/* Assert CPU power-on reset */
mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Remove power from the CPU */
sunxi_cpu_disable_power(cluster, core);
} else {
/* power down(?) debug core */
mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8));
/* ??? Activate the core output clamps, but not for core 0 */
if (core != 0) {
mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(1));
}
/* ??? Assert CPU power-on reset ??? */
mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
/* Remove power from the CPU */
sunxi_cpu_disable_power(cluster, core);
}
}
void sunxi_cpu_on(u_register_t mpidr)
@ -71,23 +92,45 @@ void sunxi_cpu_on(u_register_t mpidr)
VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
/* Assert CPU core reset */
mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
/* Assert CPU power-on reset */
mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Set CPU to start in AArch64 mode */
mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster),
BIT(SUNXI_AA64nAA32_OFFSET + core));
/* Apply power to the CPU */
sunxi_cpu_enable_power(cluster, core);
/* Release the core output clamps */
mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
/* Deassert CPU power-on reset */
mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Deassert CPU core reset */
mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
/* Assert DBGPWRDUP */
mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
if (sunxi_cpucfg_has_per_cluster_regs()) {
/* Assert CPU core reset */
mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
/* Assert CPU power-on reset */
mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Set CPU to start in AArch64 mode */
mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster),
BIT(SUNXI_AA64nAA32_OFFSET + core));
/* Apply power to the CPU */
sunxi_cpu_enable_power(cluster, core);
/* Release the core output clamps */
mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
/* Deassert CPU power-on reset */
mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Deassert CPU core reset */
mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
/* Assert DBGPWRDUP */
mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
} else {
/* Assert CPU core reset */
mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0));
/* ??? Assert CPU power-on reset ??? */
mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
/* Set CPU to start in AArch64 mode */
mmio_setbits_32(SUNXI_CPU_CTRL_REG(core), BIT(0));
/* Apply power to the CPU */
sunxi_cpu_enable_power(cluster, core);
/* ??? Release the core output clamps ??? */
mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(1));
/* ??? Deassert CPU power-on reset ??? */
mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
/* Deassert CPU core reset */
mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0));
/* power up(?) debug core */
mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8));
}
}
void sunxi_cpu_power_off_others(void)

20
plat/allwinner/common/sunxi_pm.c
View file

@ -25,6 +25,11 @@ bool sunxi_psci_is_scpi(void)
}
#endif
#ifndef SUNXI_ALT_RVBAR_LO_REG
#define SUNXI_ALT_RVBAR_LO_REG(n) 0
#define SUNXI_ALT_RVBAR_HI_REG(n) 0
#endif
int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
{
/* The non-secure entry point must be in DRAM */
@ -42,10 +47,17 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
/* Program all CPU entry points. */
for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) {
mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
sec_entrypoint & 0xffffffff);
mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
sec_entrypoint >> 32);
if (sunxi_cpucfg_has_per_cluster_regs()) {
mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
sec_entrypoint & 0xffffffff);
mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
sec_entrypoint >> 32);
} else {
mmio_write_32(SUNXI_ALT_RVBAR_LO_REG(cpu),
sec_entrypoint & 0xffffffff);
mmio_write_32(SUNXI_ALT_RVBAR_HI_REG(cpu),
sec_entrypoint >> 32);
}
}
if (sunxi_set_scpi_psci_ops(psci_ops) == 0) {

5
plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h
View file

@ -36,4 +36,9 @@
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 24
static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
{
return true;
}
#endif /* SUNXI_CPUCFG_H */

39
plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
View file

@ -1,35 +1,6 @@
/*
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <sunxi_cpucfg_ncat.h>
#ifndef SUNXI_CPUCFG_H
#define SUNXI_CPUCFG_H
#include <sunxi_mmap.h>
/* c = cluster, n = core */
#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024)
#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0)
#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
(c) * 0x10 + (n) * 4)
#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 24
#endif /* SUNXI_CPUCFG_H */
static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
{
return true;
}

1
plat/allwinner/sun50i_h6/include/sunxi_mmap.h
View file

@ -59,5 +59,6 @@
#define SUNXI_R_RSB_BASE 0x07083000
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_PIO_BASE 0x07022000
#define SUNXI_CPUSUBSYS_BASE 0x08100000
#endif /* SUNXI_MMAP_H */

39
plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
View file

@ -1,35 +1,8 @@
/*
* Copyright (c) 2017-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/common/platform.h>
#ifndef SUNXI_CPUCFG_H
#define SUNXI_CPUCFG_H
#include <sunxi_cpucfg_ncat.h>
#include <sunxi_mmap.h>
/* c = cluster, n = core */
#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024)
#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0)
#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
(c) * 0x10 + (n) * 4)
#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 24
#endif /* SUNXI_CPUCFG_H */
static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
{
return (plat_get_soc_revision() != 2);
}

1
plat/allwinner/sun50i_h616/include/sunxi_mmap.h
View file

@ -41,6 +41,7 @@
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_I2C_BASE 0x07081400
#define SUNXI_R_RSB_BASE 0x07083000
#define SUNXI_CPUSUBSYS_BASE 0x08100000
#define SUNXI_CPUCFG_BASE 0x09010000
#endif /* SUNXI_MMAP_H */

32
plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h
View file

@ -1,31 +1 @@
/*
* Copyright (c) 2021 Sipeed
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SUNXI_CPUCFG_H
#define SUNXI_CPUCFG_H
#include <sunxi_mmap.h>
/* c = cluster, n = core */
#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010)
#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014)
#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024)
#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0)
#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000)
#define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000)
#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
(c) * 0x10 + (n) * 4)
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 4
#endif /* SUNXI_CPUCFG_H */
#include <sunxi_cpucfg_ncat2.h>