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018c1d878f
The Allwinner T507 SoC is using the same die as the H616, but in a different package. On top of this, there is at least one different die revision out there, which uses a different CPU cluster control block. The same die revision has been spotted in some, but not all, H313 SoCs. Apart from that IP block, the rest of the SoC seems the same, so we can support them using the existing H616 port. The die revision can be auto-detected, so there is no extra build option or knowledge needed. Provide the deviating CPU power up/down sequence for the die variant. The new IP block uses per-core instead of per-cluster registers, but follows the same pattern otherwise. Since the CPU ops code is shared among all Allwinner SoCs, we need to dummy-define the new register names for the older SoCs. The actual new code is guarded by a predicate function, that is hard coded to return true on the other SoCs. Since this is a static inline function in a header file, the compiler will optimise away the unneeded branch there, so the generated code for the other SoCs stays the same. Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <common/fdt_fixup.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_private.h>
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static bool psci_is_scpi;
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#if SUNXI_PSCI_USE_SCPI
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bool sunxi_psci_is_scpi(void)
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{
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return psci_is_scpi;
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}
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#endif
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#ifndef SUNXI_ALT_RVBAR_LO_REG
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#define SUNXI_ALT_RVBAR_LO_REG(n) 0
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#define SUNXI_ALT_RVBAR_HI_REG(n) 0
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#endif
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int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
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{
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/* The non-secure entry point must be in DRAM */
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if (ns_entrypoint < SUNXI_DRAM_BASE) {
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return PSCI_E_INVALID_ADDRESS;
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}
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return PSCI_E_SUCCESS;
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}
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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assert(psci_ops);
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/* Program all CPU entry points. */
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for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) {
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if (sunxi_cpucfg_has_per_cluster_regs()) {
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mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
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sec_entrypoint & 0xffffffff);
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mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
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sec_entrypoint >> 32);
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} else {
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mmio_write_32(SUNXI_ALT_RVBAR_LO_REG(cpu),
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sec_entrypoint & 0xffffffff);
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mmio_write_32(SUNXI_ALT_RVBAR_HI_REG(cpu),
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sec_entrypoint >> 32);
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}
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}
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if (sunxi_set_scpi_psci_ops(psci_ops) == 0) {
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INFO("PSCI: Suspend is available via SCPI\n");
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psci_is_scpi = true;
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} else {
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INFO("PSCI: Suspend is unavailable\n");
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sunxi_set_native_psci_ops(psci_ops);
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}
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return 0;
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}
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