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stm32mp1: save boot information in backup registers
This will be used by BL33 to get boot device and instance. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
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5 changed files with 80 additions and 0 deletions
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@ -19,6 +19,7 @@
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#include <stm32mp1_clk.h>
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#include <stm32mp1_dt.h>
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#include <stm32mp1_private.h>
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#include <stm32mp1_context.h>
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#include <stm32mp1_pwr.h>
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#include <stm32mp1_rcc.h>
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#include <string.h>
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@ -37,6 +38,9 @@ void bl2_platform_setup(void)
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void bl2_el3_plat_arch_setup(void)
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{
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boot_api_context_t *boot_context =
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(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
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/*
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* Disable the backup domain write protection.
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* The protection is enable at each reset by hardware
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@ -90,5 +94,11 @@ void bl2_el3_plat_arch_setup(void)
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panic();
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}
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if (stm32_save_boot_interface(boot_context->boot_interface_selected,
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boot_context->boot_interface_instance) !=
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0) {
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ERROR("Cannot save boot interface\n");
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}
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stm32mp1_io_setup();
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}
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14
plat/st/stm32mp1/include/stm32mp1_context.h
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14
plat/st/stm32mp1/include/stm32mp1_context.h
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@ -0,0 +1,14 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __STM32MP1_CONTEXT_H__
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#define __STM32MP1_CONTEXT_H__
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#include <stdint.h>
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int stm32_save_boot_interface(uint32_t interface, uint32_t instance);
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#endif /* __STM32MP1_CONTEXT_H__ */
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@ -43,6 +43,7 @@ PLAT_BL_COMMON_SOURCES += ${LIBFDT_SRCS} \
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drivers/st/clk/stm32mp1_clkfunc.c \
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drivers/st/gpio/stm32_gpio.c \
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drivers/st/reset/stm32mp1_reset.c \
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plat/st/stm32mp1/stm32mp1_context.c \
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plat/st/stm32mp1/stm32mp1_dt.c \
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plat/st/stm32mp1/stm32mp1_helper.S
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42
plat/st/stm32mp1/stm32mp1_context.c
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42
plat/st/stm32mp1/stm32mp1_context.c
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <errno.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include <stm32mp1_clk.h>
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#include <stm32mp1_context.h>
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#define TAMP_BOOT_ITF_BACKUP_REG_ID U(20)
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#define TAMP_BOOT_ITF_MASK U(0x0000FF00)
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#define TAMP_BOOT_ITF_SHIFT 8
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int stm32_save_boot_interface(uint32_t interface, uint32_t instance)
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{
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uint32_t tamp_clk_off = 0;
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uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
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if (!stm32mp1_clk_is_enabled(RTCAPB)) {
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tamp_clk_off = 1;
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if (stm32mp1_clk_enable(RTCAPB) != 0) {
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return -EINVAL;
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}
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}
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mmio_clrsetbits_32(bkpr_itf_idx,
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TAMP_BOOT_ITF_MASK,
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((interface << 4) | (instance & 0xFU)) <<
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TAMP_BOOT_ITF_SHIFT);
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if (tamp_clk_off != 0U) {
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if (stm32mp1_clk_disable(RTCAPB) != 0) {
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return -EINVAL;
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}
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}
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return 0;
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}
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@ -157,6 +157,19 @@ enum ddr_type {
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#define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/
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#define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/
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/*******************************************************************************
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* STM32MP1 TAMP
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******************************************************************************/
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#define TAMP_BASE U(0x5C00A000)
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#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
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#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
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static inline uint32_t tamp_bkpr(uint32_t idx)
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{
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return TAMP_BKP_REGISTER_BASE + (idx << 2);
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}
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#endif
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/*******************************************************************************
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* STM32MP1 DDRCTRL
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******************************************************************************/
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