mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
e58a53fb72
This will be used by BL33 to get boot device and instance. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
188 lines
6.3 KiB
C
188 lines
6.3 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_DEF_H
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#define STM32MP1_DEF_H
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#include <tbbr_img_def.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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/*******************************************************************************
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* STM32MP1 memory map related constants
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******************************************************************************/
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#define STM32MP1_SRAM_BASE U(0x2FFC0000)
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#define STM32MP1_SRAM_SIZE U(0x00040000)
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/* DDR configuration */
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#define STM32MP1_DDR_BASE U(0xC0000000)
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#define STM32MP1_DDR_SIZE_DFLT U(0x20000000) /* 512 MB */
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#define STM32MP1_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
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#define STM32MP1_DDR_SPEED_DFLT 528
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/* DDR power initializations */
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#ifndef __ASSEMBLY__
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enum ddr_type {
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STM32MP_DDR3,
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STM32MP_LPDDR2,
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};
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#endif
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/* Section used inside TF binaries */
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#define STM32MP1_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */
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/* 256 Octets reserved for header */
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#define STM32MP1_HEADER_SIZE U(0x00000100)
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#define STM32MP1_BINARY_BASE (STM32MP1_SRAM_BASE + \
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STM32MP1_PARAM_LOAD_SIZE + \
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STM32MP1_HEADER_SIZE)
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#define STM32MP1_BINARY_SIZE (STM32MP1_SRAM_SIZE - \
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(STM32MP1_PARAM_LOAD_SIZE + \
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STM32MP1_HEADER_SIZE))
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#if STACK_PROTECTOR_ENABLED
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#define STM32MP1_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */
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#else
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#define STM32MP1_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */
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#endif
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#define STM32MP1_BL32_BASE (STM32MP1_SRAM_BASE + \
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STM32MP1_SRAM_SIZE - \
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STM32MP1_BL32_SIZE)
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#if STACK_PROTECTOR_ENABLED
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#define STM32MP1_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */
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#else
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#define STM32MP1_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */
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#endif
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#define STM32MP1_BL2_BASE (STM32MP1_BL32_BASE - \
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STM32MP1_BL2_SIZE)
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/* BL2 and BL32/sp_min require 5 tables */
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#define MAX_XLAT_TABLES 5
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
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*/
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#define MAX_MMAP_REGIONS 11
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/* DTB initialization value */
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#define STM32MP1_DTB_SIZE U(0x00004000) /* 16Ko for DTB */
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#define STM32MP1_DTB_BASE (STM32MP1_BL2_BASE - \
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STM32MP1_DTB_SIZE)
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#define STM32MP1_BL33_BASE (STM32MP1_DDR_BASE + U(0x100000))
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/*******************************************************************************
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* STM32MP1 device/io map related constants (used for MMU)
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******************************************************************************/
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#define STM32MP1_DEVICE1_BASE U(0x40000000)
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#define STM32MP1_DEVICE1_SIZE U(0x40000000)
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#define STM32MP1_DEVICE2_BASE U(0x80000000)
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#define STM32MP1_DEVICE2_SIZE U(0x40000000)
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/*******************************************************************************
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* STM32MP1 RCC
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******************************************************************************/
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#define RCC_BASE U(0x50000000)
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/*******************************************************************************
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* STM32MP1 PWR
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******************************************************************************/
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#define PWR_BASE U(0x50001000)
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/*******************************************************************************
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* STM32MP1 UART
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******************************************************************************/
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#define USART1_BASE U(0x5C000000)
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#define USART2_BASE U(0x4000E000)
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#define USART3_BASE U(0x4000F000)
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#define UART4_BASE U(0x40010000)
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#define UART5_BASE U(0x40011000)
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#define USART6_BASE U(0x44003000)
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#define UART7_BASE U(0x40018000)
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#define UART8_BASE U(0x40019000)
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#define STM32MP1_DEBUG_USART_BASE UART4_BASE
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#define STM32MP1_UART_BAUDRATE 115200
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/*******************************************************************************
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* STM32MP1 GIC-400
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******************************************************************************/
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#define STM32MP1_GICD_BASE U(0xA0021000)
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#define STM32MP1_GICC_BASE U(0xA0022000)
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#define STM32MP1_GICH_BASE U(0xA0024000)
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#define STM32MP1_GICV_BASE U(0xA0026000)
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/*******************************************************************************
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* STM32MP1 TZC (TZ400)
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******************************************************************************/
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#define STM32MP1_TZC_BASE U(0x5C006000)
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#define STM32MP1_TZC_A7_ID U(0)
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#define STM32MP1_TZC_LCD_ID U(3)
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#define STM32MP1_TZC_GPU_ID U(4)
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#define STM32MP1_TZC_MDMA_ID U(5)
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#define STM32MP1_TZC_DMA_ID U(6)
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#define STM32MP1_TZC_USB_HOST_ID U(7)
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#define STM32MP1_TZC_USB_OTG_ID U(8)
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#define STM32MP1_TZC_SDMMC_ID U(9)
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#define STM32MP1_TZC_ETH_ID U(10)
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#define STM32MP1_TZC_DAP_ID U(15)
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#define STM32MP1_MEMORY_NS 0
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#define STM32MP1_MEMORY_SECURE 1
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#define STM32MP1_FILTER_BIT_ALL 3
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/*******************************************************************************
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* STM32MP1 SDMMC
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******************************************************************************/
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#define STM32MP1_SDMMC1_BASE U(0x58005000)
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#define STM32MP1_SDMMC2_BASE U(0x58007000)
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#define STM32MP1_SDMMC3_BASE U(0x48004000)
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#define STM32MP1_SD_INIT_FREQ 400000 /*400 KHz*/
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#define STM32MP1_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/
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#define STM32MP1_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/
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#define STM32MP1_EMMC_INIT_FREQ STM32MP1_SD_INIT_FREQ
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#define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/
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#define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/
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/*******************************************************************************
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* STM32MP1 TAMP
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******************************************************************************/
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#define TAMP_BASE U(0x5C00A000)
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#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
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#if !(defined(__LINKER__) || defined(__ASSEMBLY__))
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static inline uint32_t tamp_bkpr(uint32_t idx)
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{
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return TAMP_BKP_REGISTER_BASE + (idx << 2);
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}
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#endif
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/*******************************************************************************
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* STM32MP1 DDRCTRL
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******************************************************************************/
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#define DDRCTRL_BASE U(0x5A003000)
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/*******************************************************************************
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* STM32MP1 DDRPHYC
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******************************************************************************/
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#define DDRPHYC_BASE U(0x5A004000)
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/*******************************************************************************
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* STM32MP1 I2C4
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******************************************************************************/
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#define I2C4_BASE U(0x5C002000)
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#endif /* STM32MP1_DEF_H */
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