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Merge changes If7dec725,Iedcb84a7,Ife0a4bec into integration
* changes: errata: workaround for Cortex-A78 erratum 2132060 errata: workaround for Neoverse-V1 erratum 2108267 fix(errata): workaround for Neoverse-N2 erratum 2138953
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
e2f4b434b0
8 changed files with 169 additions and 15 deletions
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@ -284,6 +284,10 @@ For Cortex-A78, the following errata build flags are defined :
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- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
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CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
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- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
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CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
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is still open.
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For Cortex-A78 AE, the following errata build flags are defined :
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- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78
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@ -371,6 +375,10 @@ For Neoverse V1, the following errata build flags are defined :
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CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
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CPU. It is still open.
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- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
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CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
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It is still open.
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For Cortex-A710, the following errata build flags are defined :
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- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
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@ -407,6 +415,9 @@ For Neoverse N2, the following errata build flags are defined :
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- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
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CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
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DSU Errata Workarounds
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----------------------
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@ -16,6 +16,9 @@
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******************************************************************************/
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#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
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#define CPUECTLR_EL1_PF_MODE_LSB U(6)
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#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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@ -8,37 +8,45 @@
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#define NEOVERSE_N2_H
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/* Neoverse N2 ID register for revision r0p0 */
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#define NEOVERSE_N2_MIDR U(0x410FD490)
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#define NEOVERSE_N2_MIDR U(0x410FD490)
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/*******************************************************************************
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* CPU Power control register
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******************************************************************************/
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#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
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#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
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#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
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#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
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#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
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#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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#endif /* NEOVERSE_N2_H */
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@ -15,6 +15,9 @@
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#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
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#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
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#define CPUECTLR_EL1_PF_MODE_LSB U(6)
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#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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@ -198,6 +198,35 @@ func check_errata_1952683
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b cpu_rev_var_ls
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endfunc check_errata_1952683
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata 2132060.
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* This applies to revisions r0p0, r1p0, r1p1, and r1p2.
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* It is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_a78_2132060_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2132060
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cbz x0, 1f
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/* Apply the workaround. */
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mrs x1, CORTEX_A78_CPUECTLR_EL1
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mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
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bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
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msr CORTEX_A78_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a78_2132060_wa
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func check_errata_2132060
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/* Applies to r0p0, r0p1, r1p1, and r1p2 */
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mov x1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_2132060
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78
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* -------------------------------------------------
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@ -232,6 +261,11 @@ func cortex_a78_reset_func
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bl errata_a78_1952683_wa
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#endif
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#if ERRATA_A78_2132060
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mov x0, x18
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bl errata_a78_2132060_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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@ -291,6 +325,7 @@ func cortex_a78_errata_report
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report_errata ERRATA_A78_1951500, cortex_a78, 1951500
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report_errata ERRATA_A78_1821534, cortex_a78, 1821534
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report_errata ERRATA_A78_1952683, cortex_a78, 1952683
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report_errata ERRATA_A78_2132060, cortex_a78, 2132060
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ldp x8, x30, [sp], #16
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ret
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@ -183,6 +183,35 @@ func check_errata_2138956
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b cpu_rev_var_ls
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endfunc check_errata_2138956
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N2 Erratum 2138953.
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* This applies to revision r0p0 of Neoverse N2. it is still open.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_n2_2138953_wa
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/* Check revision. */
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mov x17, x30
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bl check_errata_2138953
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cbz x0, 1f
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/* Apply instruction patching sequence */
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mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
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mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
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bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
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msr NEOVERSE_N2_CPUECTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_n2_2138953_wa
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func check_errata_2138953
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/* Applies to r0p0 */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_2138953
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/* -------------------------------------------
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* The CPU Ops reset function for Neoverse N2.
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* -------------------------------------------
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@ -224,6 +253,11 @@ func neoverse_n2_reset_func
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bl errata_n2_2138956_wa
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#endif
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#if ERRATA_N2_2138953
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mov x0, x18
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bl errata_n2_2138953_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, cptr_el3
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@ -287,8 +321,9 @@ func neoverse_n2_errata_report
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report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
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report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
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report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
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report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
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report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
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report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
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report_errata ERRATA_N2_2138953, neoverse_n2, 2138953
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ldp x8, x30, [sp], #16
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ret
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@ -259,6 +259,35 @@ func check_errata_2139242
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b cpu_rev_var_ls
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endfunc check_errata_2139242
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #2108267.
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* This applies to revisions r0p0, r1p0, and r1p1, it
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* is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x1, x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_2108267_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2108267
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cbz x0, 1f
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/* Apply the workaround. */
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mrs x1, NEOVERSE_V1_CPUECTLR_EL1
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mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
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bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
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msr NEOVERSE_V1_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_neoverse_v1_2108267_wa
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func check_errata_2108267
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/* Applies to r0p0, r1p0, r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_2108267
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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@ -296,6 +325,7 @@ func neoverse_v1_errata_report
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report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
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report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
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report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
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report_errata ERRATA_V1_2108267, neoverse_v1, 2108267
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ldp x8, x30, [sp], #16
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ret
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@ -344,6 +374,11 @@ func neoverse_v1_reset_func
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bl errata_neoverse_v1_2139242_wa
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#endif
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#if ERRATA_V1_2108267
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mov x0, x18
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bl errata_neoverse_v1_2108267_wa
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#endif
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ret x19
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endfunc neoverse_v1_reset_func
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@ -327,6 +327,10 @@ ERRATA_A78_1821534 ?=0
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# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0.
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ERRATA_A78_1952683 ?=0
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# Flag to apply erratum 2132060 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
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ERRATA_A78_2132060 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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ERRATA_N1_1043202 ?=0
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@ -411,11 +415,15 @@ ERRATA_V1_1940577 ?=0
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# Flag to apply erratum 1966096 workaround during reset. This erratum applies
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# to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open. This issue
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# exists in r0p0 as well but there is no workaround for that revision.
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ERRATA_V1_1966096 ?=0
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ERRATA_V1_1966096 ?=0
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# Flag to apply erratum 2139242 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
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ERRATA_V1_2139242 ?=0
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ERRATA_V1_2139242 ?=0
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# Flag to apply erratum 2108267 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
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ERRATA_V1_2108267 ?=0
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# Flag to apply erratum 1987031 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
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@ -445,6 +453,10 @@ ERRATA_N2_2189731 ?=0
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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ERRATA_N2_2138956 ?=0
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# Flag to apply erratum 2138953 workaround during reset. This erratum applies
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# to revision r0p0 of the Neoverse N2 cpu and is still open.
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ERRATA_N2_2138953 ?=0
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# Flag to apply erratum 2055002 workaround during reset. This erratum applies
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# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
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ERRATA_A710_2055002 ?=0
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@ -714,6 +726,10 @@ $(eval $(call add_define,ERRATA_A78_1821534))
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$(eval $(call assert_boolean,ERRATA_A78_1952683))
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$(eval $(call add_define,ERRATA_A78_1952683))
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# Process ERRATA_A78_2132060 flag
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$(eval $(call assert_boolean,ERRATA_A78_2132060))
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$(eval $(call add_define,ERRATA_A78_2132060))
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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@ -802,6 +818,10 @@ $(eval $(call add_define,ERRATA_V1_1966096))
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$(eval $(call assert_boolean,ERRATA_V1_2139242))
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$(eval $(call add_define,ERRATA_V1_2139242))
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# Process ERRATA_V1_2108267 flag
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$(eval $(call assert_boolean,ERRATA_V1_2108267))
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$(eval $(call add_define,ERRATA_V1_2108267))
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# Process ERRATA_A710_1987031 flag
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$(eval $(call assert_boolean,ERRATA_A710_1987031))
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$(eval $(call add_define,ERRATA_A710_1987031))
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@ -830,6 +850,10 @@ $(eval $(call add_define,ERRATA_N2_2189731))
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$(eval $(call assert_boolean,ERRATA_N2_2138956))
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$(eval $(call add_define,ERRATA_N2_2138956))
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# Process ERRATA_N2_2138953 flag
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$(eval $(call assert_boolean,ERRATA_N2_2138953))
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$(eval $(call add_define,ERRATA_N2_2138953))
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# Process ERRATA_A710_2055002 flag
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$(eval $(call assert_boolean,ERRATA_A710_2055002))
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$(eval $(call add_define,ERRATA_A710_2055002))
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