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Merge changes from topic "kc/errata_refactor" into integration
* changes: refactor(cpus): convert the Cortex-A75 to use cpu helpers refactor(cpus): convert the Cortex-A75 to use the errata framework
This commit is contained in:
Lauren Wehrmeister
TrustedFirmware Code Review
commit
e2ca9af171
1 changed files with 82 additions and 168 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -15,139 +15,43 @@
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#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex A75 Errata #764081.
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* This applies only to revision r0p0 of Cortex A75.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
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sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
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workaround_reset_end cortex_a75, ERRATUM(764081)
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check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0)
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workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748
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sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13)
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workaround_reset_end cortex_a75, ERRATUM(790748)
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check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0)
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/* ERRATA_DSU_798953 :
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* The errata is defined in dsu_helpers.S but applies to cortex_a75
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* as well. Henceforth creating symbolic names to the already existing errata
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* workaround functions to get them registered under the Errata Framework.
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*/
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func errata_a75_764081_wa
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/*
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* Compare x0 against revision r0p0
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.equ check_erratum_cortex_a75_798953, check_errata_dsu_798953
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.equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa
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add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
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/* ERRATA_DSU_936184 :
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* The errata is defined in dsu_helpers.S but applies to cortex_a75
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* as well. Henceforth creating symbolic names to the already existing errata
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* workaround functions to get them registered under the Errata Framework.
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*/
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mov x17, x30
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bl check_errata_764081
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cbz x0, 1f
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mrs x1, sctlr_el3
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orr x1, x1 ,#SCTLR_IESB_BIT
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msr sctlr_el3, x1
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isb
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1:
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ret x17
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endfunc errata_a75_764081_wa
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.equ check_erratum_cortex_a75_936184, check_errata_dsu_936184
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.equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa
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add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
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func check_errata_764081
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_764081
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workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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#if IMAGE_BL31
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override_vector_table wa_cve_2017_5715_bpiall_vbar
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a75, CVE(2017, 5715)
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/* --------------------------------------------------
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* Errata Workaround for Cortex A75 Errata #790748.
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* This applies only to revision r0p0 of Cortex A75.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a75_790748_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_790748
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cbz x0, 1f
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mrs x1, CORTEX_A75_CPUACTLR_EL1
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orr x1, x1 ,#(1 << 13)
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msr CORTEX_A75_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a75_790748_wa
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func check_errata_790748
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_790748
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A75.
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* -------------------------------------------------
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*/
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func cortex_a75_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A75_764081
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mov x0, x18
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bl errata_a75_764081_wa
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#endif
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#if ERRATA_A75_790748
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mov x0, x18
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bl errata_a75_790748_wa
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#endif
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#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
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cpu_check_csv2 x0, 1f
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adr x0, wa_cve_2017_5715_bpiall_vbar
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msr vbar_el3, x0
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isb
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/* Skip installing vector table again for CVE_2022_23960 */
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b 2f
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1:
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#if WORKAROUND_CVE_2022_23960
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adr x0, wa_cve_2017_5715_bpiall_vbar
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msr vbar_el3, x0
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isb
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#endif
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2:
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#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
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#if WORKAROUND_CVE_2018_3639
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mrs x0, CORTEX_A75_CPUACTLR_EL1
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orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
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msr CORTEX_A75_CPUACTLR_EL1, x0
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isb
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#endif
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#if ERRATA_DSU_798953
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bl errata_dsu_798953_wa
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#endif
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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#endif
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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isb
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
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msr actlr_el2, x0
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isb
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/* Enable group0 counters */
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mov x0, #CORTEX_A75_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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/* Enable group1 counters */
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mov x0, #CORTEX_A75_AMU_GROUP1_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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#endif
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ret x19
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endfunc cortex_a75_reset_func
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func check_errata_cve_2017_5715
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check_erratum_custom_start cortex_a75, CVE(2017, 5715)
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cpu_check_csv2 x0, 1f
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#if WORKAROUND_CVE_2017_5715
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mov x0, #ERRATA_APPLIES
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@ -158,18 +62,27 @@ func check_errata_cve_2017_5715
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_errata_cve_2017_5715
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check_erratum_custom_end cortex_a75, CVE(2017, 5715)
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func check_errata_cve_2018_3639
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#if WORKAROUND_CVE_2018_3639
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2018_3639
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workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
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workaround_reset_end cortex_a75, CVE(2018, 3639)
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func check_errata_cve_2022_23960
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check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/* Skip installing vector table again if already done for CVE(2017, 5715) */
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adr x0, wa_cve_2017_5715_bpiall_vbar
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mrs x1, vbar_el3
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cmp x0, x1
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b.eq 1f
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msr vbar_el3, x0
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1:
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a75, CVE(2022, 23960)
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check_erratum_custom_start cortex_a75, CVE(2022, 23960)
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#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
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cpu_check_csv2 x0, 1f
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mov x0, #ERRATA_APPLIES
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@ -184,7 +97,34 @@ func check_errata_cve_2022_23960
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#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
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mov x0, #ERRATA_MISSING
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ret
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endfunc check_errata_cve_2022_23960
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check_erratum_custom_end cortex_a75, CVE(2022, 23960)
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A75.
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* -------------------------------------------------
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*/
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cpu_reset_func_start cortex_a75
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT
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isb
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT
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isb
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/* Enable group0 counters */
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mov x0, #CORTEX_A75_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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/* Enable group1 counters */
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mov x0, #CORTEX_A75_AMU_GROUP1_MASK
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msr CPUAMCNTENSET_EL0, x0
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/* isb included in cpu_reset_func_end macro */
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#endif
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cpu_reset_func_end cortex_a75
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func check_smccc_arch_workaround_3
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mov x0, #ERRATA_APPLIES
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@ -200,39 +140,13 @@ func cortex_a75_core_pwr_dwn
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
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msr CORTEX_A75_CPUPWRCTLR_EL1, x0
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sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \
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CORTEX_A75_CORE_PWRDN_EN_MASK
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isb
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ret
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endfunc cortex_a75_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A75. Must follow AAPCS.
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*/
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func cortex_a75_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A75_764081, cortex_a75, 764081
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report_errata ERRATA_A75_790748, cortex_a75, 790748
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report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
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report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
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report_errata ERRATA_DSU_798953, cortex_a75, dsu_798953
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report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184
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report_errata WORKAROUND_CVE_2022_23960, cortex_a75, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a75_errata_report
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#endif
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errata_report_shim cortex_a75
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/* ---------------------------------------------
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* This function provides cortex_a75 specific
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@ -255,7 +169,7 @@ endfunc cortex_a75_cpu_reg_dump
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declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
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cortex_a75_reset_func, \
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check_errata_cve_2017_5715, \
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check_erratum_cortex_a75_5715, \
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CPU_NO_EXTRA2_FUNC, \
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check_smccc_arch_workaround_3, \
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cortex_a75_core_pwr_dwn
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