From 742bf3ea23f4b3e9a374aa9d3ffac01402d780fa Mon Sep 17 00:00:00 2001 From: Kathleen Capella Date: Thu, 13 Apr 2023 18:36:57 -0400 Subject: [PATCH 1/2] refactor(cpus): convert the Cortex-A75 to use the errata framework This involves replacing: * the reset_func with the standard cpu_reset_func_{start,end} to apply errata automatically * the _errata_report with the errata_report_shim to report errata automatically ...and for each erratum: * the prologue with the workaround__start to do the checks and framework registration automatically * the epilogue with the workaround__end * the checker function with the check_erratum_ to make it more descriptive It is important to note that the errata workaround sequences remain unchanged and preserve their git blame. Testing was conducted by: * Building for release with all errata flags enabled and running script in change 19136 to compare output of objdump for each errata. Only ERRATA_A75_764081 and ERRATA_A75_790748 could be verified this way, rest had to be manually verified. * Manual comparison of disassembly of converted functions with non- converted functions aarch64-none-elf-objdump -D /build/fvp/release/bl31/bl31.elf vs aarch64-none-elf-objdump -D /build/fvp/release/bl31/bl31.elf * Build for release with all errata flags enabled and run default tftf tests CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp HW_ASSISTED_COHERENCY=1 \ USE_COHERENT_MEM=0 CTX_INCLUDE_AARCH32_REGS=1 \ BL33=/home/katcap01/tf-a-tests/build/fvp/debug/tftf.bin \ ERRATA_A75_764081=1 ERRATA_A75_790748=1 WORKAROUND_CVE_2017_5715=1 \ WORKAROUND_CVE_2018_3639=1 \ ERRATA_DSU_798953=1 ERRATA_DSU_936184=1 \ WORKAROUND_CVE_2022_23960=1 \ fip all * Build for debug with all errata enabled and step through ArmDS at reset to ensure all functions are entered. Signed-off-by: Kathleen Capella Change-Id: I0cd393db825fcb5c7ddea3aa2a5934ffc4b6046e --- lib/cpus/aarch64/cortex_a75.S | 248 ++++++++++++---------------------- 1 file changed, 87 insertions(+), 161 deletions(-) diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index e22c82898..3ef72c683 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,112 +15,103 @@ #error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif - /* -------------------------------------------------- - * Errata Workaround for Cortex A75 Errata #764081. - * This applies only to revision r0p0 of Cortex A75. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a75_764081_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_764081 - cbz x0, 1f +workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 mrs x1, sctlr_el3 orr x1, x1 ,#SCTLR_IESB_BIT msr sctlr_el3, x1 - isb -1: - ret x17 -endfunc errata_a75_764081_wa +workaround_reset_end cortex_a75, ERRATUM(764081) -func check_errata_764081 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_764081 +check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) - /* -------------------------------------------------- - * Errata Workaround for Cortex A75 Errata #790748. - * This applies only to revision r0p0 of Cortex A75. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a75_790748_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_790748 - cbz x0, 1f +workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 mrs x1, CORTEX_A75_CPUACTLR_EL1 orr x1, x1 ,#(1 << 13) msr CORTEX_A75_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a75_790748_wa +workaround_reset_end cortex_a75, ERRATUM(790748) -func check_errata_790748 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_790748 +check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) + +/* ERRATA_DSU_798953 : + * The errata is defined in dsu_helpers.S but applies to cortex_a75 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a75_798953, check_errata_dsu_798953 +.equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa +add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET + +/* ERRATA_DSU_936184 : + * The errata is defined in dsu_helpers.S but applies to cortex_a75 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a75_936184, check_errata_dsu_936184 +.equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa +add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET + +workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 +#if IMAGE_BL31 + adr x0, wa_cve_2017_5715_bpiall_vbar + msr vbar_el3, x0 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a75, CVE(2017, 5715) + +check_erratum_custom_start cortex_a75, CVE(2017, 5715) + cpu_check_csv2 x0, 1f +#if WORKAROUND_CVE_2017_5715 + mov x0, #ERRATA_APPLIES +#else + mov x0, #ERRATA_MISSING +#endif + ret +1: + mov x0, #ERRATA_NOT_APPLIES + ret +check_erratum_custom_end cortex_a75, CVE(2017, 5715) + +workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + mrs x0, CORTEX_A75_CPUACTLR_EL1 + orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE + msr CORTEX_A75_CPUACTLR_EL1, x0 +workaround_reset_end cortex_a75, CVE(2018, 3639) + +check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + +workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* Skip installing vector table again if already done for CVE(2017, 5715) */ + adr x0, wa_cve_2017_5715_bpiall_vbar + mrs x1, vbar_el3 + cmp x0, x1 + b.eq 1f + msr vbar_el3, x0 +1: +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a75, CVE(2022, 23960) + +check_erratum_custom_start cortex_a75, CVE(2022, 23960) +#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 + cpu_check_csv2 x0, 1f + mov x0, #ERRATA_APPLIES + ret +1: +# if WORKAROUND_CVE_2022_23960 + mov x0, #ERRATA_APPLIES +# else + mov x0, #ERRATA_MISSING +# endif /* WORKAROUND_CVE_2022_23960 */ + ret +#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ + mov x0, #ERRATA_MISSING + ret +check_erratum_custom_end cortex_a75, CVE(2022, 23960) /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A75. * ------------------------------------------------- */ -func cortex_a75_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_A75_764081 - mov x0, x18 - bl errata_a75_764081_wa -#endif - -#if ERRATA_A75_790748 - mov x0, x18 - bl errata_a75_790748_wa -#endif - -#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) - cpu_check_csv2 x0, 1f - adr x0, wa_cve_2017_5715_bpiall_vbar - msr vbar_el3, x0 - isb - /* Skip installing vector table again for CVE_2022_23960 */ - b 2f -1: -#if WORKAROUND_CVE_2022_23960 - adr x0, wa_cve_2017_5715_bpiall_vbar - msr vbar_el3, x0 - isb -#endif -2: -#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ - -#if WORKAROUND_CVE_2018_3639 - mrs x0, CORTEX_A75_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE - msr CORTEX_A75_CPUACTLR_EL1, x0 - isb -#endif - -#if ERRATA_DSU_798953 - bl errata_dsu_798953_wa -#endif - -#if ERRATA_DSU_936184 - bl errata_dsu_936184_wa -#endif +cpu_reset_func_start cortex_a75 #if ENABLE_FEAT_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -142,49 +133,9 @@ func cortex_a75_reset_func /* Enable group1 counters */ mov x0, #CORTEX_A75_AMU_GROUP1_MASK msr CPUAMCNTENSET_EL0, x0 - isb + /* isb included in cpu_reset_func_end macro */ #endif - ret x19 -endfunc cortex_a75_reset_func - -func check_errata_cve_2017_5715 - cpu_check_csv2 x0, 1f -#if WORKAROUND_CVE_2017_5715 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -1: - mov x0, #ERRATA_NOT_APPLIES - ret -endfunc check_errata_cve_2017_5715 - -func check_errata_cve_2018_3639 -#if WORKAROUND_CVE_2018_3639 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2018_3639 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 - cpu_check_csv2 x0, 1f - mov x0, #ERRATA_APPLIES - ret -1: -# if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -# else - mov x0, #ERRATA_MISSING -# endif /* WORKAROUND_CVE_2022_23960 */ - ret -#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ - mov x0, #ERRATA_MISSING - ret -endfunc check_errata_cve_2022_23960 +cpu_reset_func_end cortex_a75 func check_smccc_arch_workaround_3 mov x0, #ERRATA_APPLIES @@ -207,32 +158,7 @@ func cortex_a75_core_pwr_dwn ret endfunc cortex_a75_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A75. Must follow AAPCS. - */ -func cortex_a75_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A75_764081, cortex_a75, 764081 - report_errata ERRATA_A75_790748, cortex_a75, 790748 - report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 - report_errata ERRATA_DSU_798953, cortex_a75, dsu_798953 - report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 - report_errata WORKAROUND_CVE_2022_23960, cortex_a75, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a75_errata_report -#endif +errata_report_shim cortex_a75 /* --------------------------------------------- * This function provides cortex_a75 specific @@ -255,7 +181,7 @@ endfunc cortex_a75_cpu_reg_dump declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ cortex_a75_reset_func, \ - check_errata_cve_2017_5715, \ + check_erratum_cortex_a75_5715, \ CPU_NO_EXTRA2_FUNC, \ check_smccc_arch_workaround_3, \ cortex_a75_core_pwr_dwn From 6fafbd56d0000d9f9254563ac92bdbab7d1becad Mon Sep 17 00:00:00 2001 From: Kathleen Capella Date: Fri, 9 Jun 2023 14:11:53 -0400 Subject: [PATCH 2/2] refactor(cpus): convert the Cortex-A75 to use cpu helpers Testing done in conjunction with change 258152. Signed-off-by: Kathleen Capella Change-Id: I9082c7a5c68e39d6e419c2a00501d63895ca73c7 --- lib/cpus/aarch64/cortex_a75.S | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index 3ef72c683..0a7b9fbb0 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -16,17 +16,13 @@ #endif workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 - mrs x1, sctlr_el3 - orr x1, x1 ,#SCTLR_IESB_BIT - msr sctlr_el3, x1 + sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT workaround_reset_end cortex_a75, ERRATUM(764081) check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 - mrs x1, CORTEX_A75_CPUACTLR_EL1 - orr x1, x1 ,#(1 << 13) - msr CORTEX_A75_CPUACTLR_EL1, x1 + sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) workaround_reset_end cortex_a75, ERRATUM(790748) check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) @@ -51,8 +47,7 @@ add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 #if IMAGE_BL31 - adr x0, wa_cve_2017_5715_bpiall_vbar - msr vbar_el3, x0 + override_vector_table wa_cve_2017_5715_bpiall_vbar #endif /* IMAGE_BL31 */ workaround_reset_end cortex_a75, CVE(2017, 5715) @@ -70,9 +65,7 @@ check_erratum_custom_start cortex_a75, CVE(2017, 5715) check_erratum_custom_end cortex_a75, CVE(2017, 5715) workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 - mrs x0, CORTEX_A75_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE - msr CORTEX_A75_CPUACTLR_EL1, x0 + sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE workaround_reset_end cortex_a75, CVE(2018, 3639) check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 @@ -114,15 +107,11 @@ check_erratum_custom_end cortex_a75, CVE(2022, 23960) cpu_reset_func_start cortex_a75 #if ENABLE_FEAT_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ - mrs x0, actlr_el3 - orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT - msr actlr_el3, x0 + sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT isb /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ - mrs x0, actlr_el2 - orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT - msr actlr_el2, x0 + sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT isb /* Enable group0 counters */ @@ -151,9 +140,8 @@ func cortex_a75_core_pwr_dwn * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK - msr CORTEX_A75_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \ + CORTEX_A75_CORE_PWRDN_EN_MASK isb ret endfunc cortex_a75_core_pwr_dwn