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Merge changes from topic "kc/errata_refactor" into integration

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* changes:
  refactor(cpus): convert the Cortex-A75 to use cpu helpers
  refactor(cpus): convert the Cortex-A75 to use the errata framework
This commit is contained in:
Lauren Wehrmeister 2023-07-10 23:10:33 +02:00 • committed by TrustedFirmware Code Review
commit e2ca9af171
1 changed files with 82 additions and 168 deletions
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256
lib/cpus/aarch64/cortex_a75.S
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -15,139 +15,43 @@
#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" #error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif #endif
/* -------------------------------------------------- workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
* Errata Workaround for Cortex A75 Errata #764081. sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
* This applies only to revision r0p0 of Cortex A75. workaround_reset_end cortex_a75, ERRATUM(764081)
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu. check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0)
* Shall clobber: x0-x17
* -------------------------------------------------- workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748
sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13)
workaround_reset_end cortex_a75, ERRATUM(790748)
check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0)
/* ERRATA_DSU_798953 :
* The errata is defined in dsu_helpers.S but applies to cortex_a75
* as well. Henceforth creating symbolic names to the already existing errata
* workaround functions to get them registered under the Errata Framework.
*/ */
func errata_a75_764081_wa .equ check_erratum_cortex_a75_798953, check_errata_dsu_798953
/* .equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa
* Compare x0 against revision r0p0 add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
/* ERRATA_DSU_936184 :
* The errata is defined in dsu_helpers.S but applies to cortex_a75
* as well. Henceforth creating symbolic names to the already existing errata
* workaround functions to get them registered under the Errata Framework.
*/ */
mov x17, x30 .equ check_erratum_cortex_a75_936184, check_errata_dsu_936184
bl check_errata_764081 .equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa
cbz x0, 1f add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
mrs x1, sctlr_el3
orr x1, x1 ,#SCTLR_IESB_BIT
msr sctlr_el3, x1
isb
1:
ret x17
endfunc errata_a75_764081_wa
func check_errata_764081 workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
mov x1, #0x00 #if IMAGE_BL31
b cpu_rev_var_ls override_vector_table wa_cve_2017_5715_bpiall_vbar
endfunc check_errata_764081 #endif /* IMAGE_BL31 */
workaround_reset_end cortex_a75, CVE(2017, 5715)
/* -------------------------------------------------- check_erratum_custom_start cortex_a75, CVE(2017, 5715)
* Errata Workaround for Cortex A75 Errata #790748.
* This applies only to revision r0p0 of Cortex A75.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a75_790748_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_790748
cbz x0, 1f
mrs x1, CORTEX_A75_CPUACTLR_EL1
orr x1, x1 ,#(1 << 13)
msr CORTEX_A75_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a75_790748_wa
func check_errata_790748
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_790748
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A75.
* -------------------------------------------------
*/
func cortex_a75_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A75_764081
mov x0, x18
bl errata_a75_764081_wa
#endif
#if ERRATA_A75_790748
mov x0, x18
bl errata_a75_790748_wa
#endif
#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
isb
/* Skip installing vector table again for CVE_2022_23960 */
b 2f
1:
#if WORKAROUND_CVE_2022_23960
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
isb
#endif
2:
#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
#if WORKAROUND_CVE_2018_3639
mrs x0, CORTEX_A75_CPUACTLR_EL1
orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
msr CORTEX_A75_CPUACTLR_EL1, x0
isb
#endif
#if ERRATA_DSU_798953
bl errata_dsu_798953_wa
#endif
#if ERRATA_DSU_936184
bl errata_dsu_936184_wa
#endif
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
msr actlr_el3, x0
isb
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
mrs x0, actlr_el2
orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
msr actlr_el2, x0
isb
/* Enable group0 counters */
mov x0, #CORTEX_A75_AMU_GROUP0_MASK
msr CPUAMCNTENSET_EL0, x0
isb
/* Enable group1 counters */
mov x0, #CORTEX_A75_AMU_GROUP1_MASK
msr CPUAMCNTENSET_EL0, x0
isb
#endif
ret x19
endfunc cortex_a75_reset_func
func check_errata_cve_2017_5715
cpu_check_csv2 x0, 1f cpu_check_csv2 x0, 1f
#if WORKAROUND_CVE_2017_5715 #if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES mov x0, #ERRATA_APPLIES
@ -158,18 +62,27 @@ func check_errata_cve_2017_5715
1: 1:
mov x0, #ERRATA_NOT_APPLIES mov x0, #ERRATA_NOT_APPLIES
ret ret
endfunc check_errata_cve_2017_5715 check_erratum_custom_end cortex_a75, CVE(2017, 5715)
func check_errata_cve_2018_3639 workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
#if WORKAROUND_CVE_2018_3639 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
mov x0, #ERRATA_APPLIES workaround_reset_end cortex_a75, CVE(2018, 3639)
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2018_3639
func check_errata_cve_2022_23960 check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/* Skip installing vector table again if already done for CVE(2017, 5715) */
adr x0, wa_cve_2017_5715_bpiall_vbar
mrs x1, vbar_el3
cmp x0, x1
b.eq 1f
msr vbar_el3, x0
1:
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_a75, CVE(2022, 23960)
check_erratum_custom_start cortex_a75, CVE(2022, 23960)
#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 #if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
cpu_check_csv2 x0, 1f cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES mov x0, #ERRATA_APPLIES
@ -184,7 +97,34 @@ func check_errata_cve_2022_23960
#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
mov x0, #ERRATA_MISSING mov x0, #ERRATA_MISSING
ret ret
endfunc check_errata_cve_2022_23960 check_erratum_custom_end cortex_a75, CVE(2022, 23960)
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A75.
* -------------------------------------------------
*/
cpu_reset_func_start cortex_a75
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT
isb
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT
isb
/* Enable group0 counters */
mov x0, #CORTEX_A75_AMU_GROUP0_MASK
msr CPUAMCNTENSET_EL0, x0
isb
/* Enable group1 counters */
mov x0, #CORTEX_A75_AMU_GROUP1_MASK
msr CPUAMCNTENSET_EL0, x0
/* isb included in cpu_reset_func_end macro */
#endif
cpu_reset_func_end cortex_a75
func check_smccc_arch_workaround_3 func check_smccc_arch_workaround_3
mov x0, #ERRATA_APPLIES mov x0, #ERRATA_APPLIES
@ -200,39 +140,13 @@ func cortex_a75_core_pwr_dwn
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------- * ---------------------------------------------
*/ */
mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \
orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK CORTEX_A75_CORE_PWRDN_EN_MASK
msr CORTEX_A75_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_a75_core_pwr_dwn endfunc cortex_a75_core_pwr_dwn
#if REPORT_ERRATA errata_report_shim cortex_a75
/*
* Errata printing function for Cortex A75. Must follow AAPCS.
*/
func cortex_a75_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A75_764081, cortex_a75, 764081
report_errata ERRATA_A75_790748, cortex_a75, 790748
report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
report_errata ERRATA_DSU_798953, cortex_a75, dsu_798953
report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184
report_errata WORKAROUND_CVE_2022_23960, cortex_a75, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a75_errata_report
#endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides cortex_a75 specific * This function provides cortex_a75 specific
@ -255,7 +169,7 @@ endfunc cortex_a75_cpu_reg_dump
declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
cortex_a75_reset_func, \ cortex_a75_reset_func, \
check_errata_cve_2017_5715, \ check_erratum_cortex_a75_5715, \
CPU_NO_EXTRA2_FUNC, \ CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \ check_smccc_arch_workaround_3, \
cortex_a75_core_pwr_dwn cortex_a75_core_pwr_dwn