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Merge changes I105cd219,Ie870a7f3 into integration

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* changes:
  feat(tc): add SLC MSC nodes to TC4 DT
  refactor(tc): clarify msc0 DT node
This commit is contained in:
Olivier Deprez 2025-02-04 11:53:59 +01:00 • committed by TrustedFirmware Code Review
commit dd5e4f998a
4 changed files with 46 additions and 4 deletions
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4
fdts/tc-base.dtsi
View file

@ -615,9 +615,9 @@
* L3 cache in the DSU is the Memory System Component (MSC) * L3 cache in the DSU is the Memory System Component (MSC)
* The MPAM registers are accessed through utility bus in the DSU * The MPAM registers are accessed through utility bus in the DSU
*/ */
msc0 { dsu-msc0 {
compatible = "arm,mpam-msc"; compatible = "arm,mpam-msc";
reg = <MPAM_ADDR 0x0 0x2000>; reg = <DSU_MPAM_ADDR 0x0 0x2000>;
}; };
ete0 { ete0 {

2
fdts/tc2.dts
View file

@ -35,7 +35,7 @@
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu" #define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu" #define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ #define DSU_MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define DPU_ADDR 2cc00000 #define DPU_ADDR 2cc00000
#define DPU_IRQ 69 #define DPU_IRQ 69

2
fdts/tc3-4-base.dtsi
View file

@ -17,7 +17,7 @@
#define MHU_RX_INT_NUM 300 #define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined" #define MHU_RX_INT_NAME "combined"
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ #define DSU_MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#if TARGET_FLAVOUR_FVP #if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000 #define DPU_ADDR 4000000000

42
fdts/tc4.dts
View file

@ -104,4 +104,46 @@
compatible = "arm,coresight-pmu"; compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>; reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>;
}; };
#if defined(TARGET_FLAVOUR_FPGA)
slc-msc@0 {
compatible = "arm,mpam-msc";
reg = <0x0 MCN_MPAM_NS_BASE_ADDR(0) 0x0 0x4000>;
};
slc-msc@1 {
compatible = "arm,mpam-msc";
reg = <0x0 MCN_MPAM_NS_BASE_ADDR(1) 0x0 0x4000>;
};
slc-msc@2 {
compatible = "arm,mpam-msc";
reg = <0x0 MCN_MPAM_NS_BASE_ADDR(2) 0x0 0x4000>;
};
slc-msc@3 {
compatible = "arm,mpam-msc";
reg = <0x0 MCN_MPAM_NS_BASE_ADDR(3) 0x0 0x4000>;
};
slc-msc@4 {
compatible = "arm,mpam-msc";
reg = <0x0 MCN_MPAM_NS_BASE_ADDR(4) 0x0 0x4000>;
};
slc-msc@5 {
compatible = "arm,mpam-msc";
reg = <0x0 MCN_MPAM_NS_BASE_ADDR(5) 0x0 0x4000>;
};
slc-msc@6 {
compatible = "arm,mpam-msc";
reg = <0x0 MCN_MPAM_NS_BASE_ADDR(6) 0x0 0x4000>;
};
slc-msc@7 {
compatible = "arm,mpam-msc";
reg = <0x0 MCN_MPAM_NS_BASE_ADDR(7) 0x0 0x4000>;
};
#endif /* TARGET_FLAVOUR_FPGA */
}; };