From 967999d0d998d89ae333754c278dff8cedae2666 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Wed, 28 Aug 2024 11:46:35 +0100 Subject: [PATCH 1/2] refactor(tc): clarify msc0 DT node This node specifies the location of the MPAM registers for the DSU. Rename the node to clarify this. Signed-off-by: Jackson Cooper-Driver Signed-off-by: Icen.Zeyada Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4 --- fdts/tc-base.dtsi | 4 ++-- fdts/tc2.dts | 2 +- fdts/tc3-4-base.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 691a3b8c0..462379006 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -615,9 +615,9 @@ * L3 cache in the DSU is the Memory System Component (MSC) * The MPAM registers are accessed through utility bus in the DSU */ - msc0 { + dsu-msc0 { compatible = "arm,mpam-msc"; - reg = ; + reg = ; }; ete0 { diff --git a/fdts/tc2.dts b/fdts/tc2.dts index 003efdc90..8aa77ce86 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -35,7 +35,7 @@ #define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu" #define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu" -#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ +#define DSU_MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */ #define DPU_ADDR 2cc00000 #define DPU_IRQ 69 diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi index 049a4c643..ef8713a5c 100644 --- a/fdts/tc3-4-base.dtsi +++ b/fdts/tc3-4-base.dtsi @@ -17,7 +17,7 @@ #define MHU_RX_INT_NUM 300 #define MHU_RX_INT_NAME "combined" -#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ +#define DSU_MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ #if TARGET_FLAVOUR_FVP #define DPU_ADDR 4000000000 From 99f6790cb9681d0a2960f8d30d82c20db19f6ab7 Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Wed, 28 Aug 2024 11:44:16 +0100 Subject: [PATCH 2/2] feat(tc): add SLC MSC nodes to TC4 DT These specify the addresses of the MPAM registers in the MCN block. Note that these are enabled for TC4 FPGA only as the MPAM devices are not available on FVP. Signed-off-by: Jackson Cooper-Driver Signed-off-by: Icen.Zeyada Change-Id: I105cd21952c2bd4fac5a06c84c0a93217b5e1312 --- fdts/tc4.dts | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/fdts/tc4.dts b/fdts/tc4.dts index 98cfea16f..675c39b11 100644 --- a/fdts/tc4.dts +++ b/fdts/tc4.dts @@ -104,4 +104,46 @@ compatible = "arm,coresight-pmu"; reg = <0x0 MCN_PMU_ADDR(7) 0x0 0xffc>; }; + +#if defined(TARGET_FLAVOUR_FPGA) + slc-msc@0 { + compatible = "arm,mpam-msc"; + reg = <0x0 MCN_MPAM_NS_BASE_ADDR(0) 0x0 0x4000>; + }; + + slc-msc@1 { + compatible = "arm,mpam-msc"; + reg = <0x0 MCN_MPAM_NS_BASE_ADDR(1) 0x0 0x4000>; + }; + + slc-msc@2 { + compatible = "arm,mpam-msc"; + reg = <0x0 MCN_MPAM_NS_BASE_ADDR(2) 0x0 0x4000>; + }; + + slc-msc@3 { + compatible = "arm,mpam-msc"; + reg = <0x0 MCN_MPAM_NS_BASE_ADDR(3) 0x0 0x4000>; + }; + + slc-msc@4 { + compatible = "arm,mpam-msc"; + reg = <0x0 MCN_MPAM_NS_BASE_ADDR(4) 0x0 0x4000>; + }; + + slc-msc@5 { + compatible = "arm,mpam-msc"; + reg = <0x0 MCN_MPAM_NS_BASE_ADDR(5) 0x0 0x4000>; + }; + + slc-msc@6 { + compatible = "arm,mpam-msc"; + reg = <0x0 MCN_MPAM_NS_BASE_ADDR(6) 0x0 0x4000>; + }; + + slc-msc@7 { + compatible = "arm,mpam-msc"; + reg = <0x0 MCN_MPAM_NS_BASE_ADDR(7) 0x0 0x4000>; + }; +#endif /* TARGET_FLAVOUR_FPGA */ };