Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-17 18:14:24 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(cpus): workaround for Cortex-X4 erratum 3076789

Browse source 
Cortex-X4 erratum 3076789 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set chicken bits CPUACTLR3_EL1[14:13]=0b11
and CPUACTLR_EL1[52] = 1.
Expected performance degradation is < 0.5%, but isolated
benchmark components might see higher impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: Ib100bfab91efdb6330fdcdac127bcc5732d59196
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
This commit is contained in:
Ryan Everett 2024-05-21 11:56:37 +01:00
parent ba790730ea
commit db7eb68817
4 changed files with 16 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
docs/design/cpu-specific-build-macros.rst
View file

@ -843,6 +843,9 @@ For Cortex-X4, the following errata build flags are defined :
- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4 - ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
For Cortex-A510, the following errata build flags are defined : For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

1
include/lib/cpus/aarch64/cortex_x4.h
View file

@ -26,6 +26,7 @@
/******************************************************************************* /*******************************************************************************
* CPU Auxiliary control register specific definitions * CPU Auxiliary control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_X4_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2 #define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
#define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3 #define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3

8
lib/cpus/aarch64/cortex_x4.S
View file

@ -75,6 +75,14 @@ workaround_reset_end cortex_x4, ERRATUM(2897503)
check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1) check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789
sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14)
sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13)
sysreg_bit_set CORTEX_X4_CPUACTLR_EL1, BIT(52)
workaround_reset_end cortex_x4, ERRATUM(3076789)
check_erratum_ls cortex_x4, ERRATUM(3076789), CPU_REV(0, 1)
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31 #if IMAGE_BL31
/* /*

4
lib/cpus/cpu-ops.mk
View file

@ -843,6 +843,10 @@ CPU_FLAG_LIST += ERRATA_X4_2816013
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2. # to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2897503 CPU_FLAG_LIST += ERRATA_X4_2897503
# Flag to apply erratum 3076789 workaround on reset. This erratum applies
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_3076789
# Flag to apply erratum 1922240 workaround during reset. This erratum applies # Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240 CPU_FLAG_LIST += ERRATA_A510_1922240