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db7eb68817
Cortex-X4 erratum 3076789 is a Cat B erratum that is present in revisions r0p0, r0p1 and is fixed in r0p2. The workaround is to set chicken bits CPUACTLR3_EL1[14:13]=0b11 and CPUACTLR_EL1[52] = 1. Expected performance degradation is < 0.5%, but isolated benchmark components might see higher impact. SDEN documentation: https://developer.arm.com/documentation/SDEN2432808/latest Change-Id: Ib100bfab91efdb6330fdcdac127bcc5732d59196 Signed-off-by: Ryan Everett <ryan.everett@arm.com>
50 lines
1.8 KiB
C
50 lines
1.8 KiB
C
/*
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* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X4_H
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#define CORTEX_X4_H
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#define CORTEX_X4_MIDR U(0x410FD821)
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/* Cortex X4 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X4_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define CORTEX_X4_CPUACTLR4_EL1 S3_0_C15_C1_3
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/*******************************************************************************
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* CPU Auxiliary control register 5 specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14)
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#ifndef __ASSEMBLER__
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#if ERRATA_X4_2726228
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long check_erratum_cortex_x4_2726228(long cpu_rev);
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#else
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static inline long check_erratum_cortex_x4_2726228(long cpu_rev)
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{
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return 0;
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}
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#endif /* ERRATA_X4_2726228 */
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_X4_H */
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