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refactor(cpufeat): enable FEAT_NV2 for FEAT_STATE_CHECKED

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At the moment we only support for FEAT_NV2 to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (CTX_INCLUDE_NEVE_REGS=2), by
splitting get_armv8_4_feat_nv_support() into an ID register reading
function and a second function to report the support status. That
function considers both build time settings and runtime information
(if needed), and is used before we access the VNCR_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_nv2_supported() function to guard its execution.

Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.

Change-Id: I85b080641995fb72cfd4ac933f7a3f75770c2cb9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2023-01-27 14:09:20 +00:00
parent 1223d2a020
commit d5384b69d1
8 changed files with 30 additions and 50 deletions
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15
common/feat_detect.c
View file

@ -90,18 +90,6 @@ static void read_feat_dit(void)
#endif
}
/**************************************************************
* Feature : FEAT_NV2 (Enhanced Nested Virtualization Support)
*************************************************************/
static void read_feat_nv2(void)
{
#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS)
unsigned int nv = get_armv8_4_feat_nv_support();
feat_detect_panic((nv == ID_AA64MMFR2_EL1_NV2_SUPPORTED), "NV2");
#endif
}
/***********************************
* Feature : FEAT_SEL2 (Secure EL2)
**********************************/
@ -223,7 +211,8 @@ void detect_arch_features(void)
"AMUv1", 1, 2);
check_feature(ENABLE_MPAM_FOR_LOWER_ELS, read_feat_mpam_version(),
"MPAM", 1, 17);
read_feat_nv2();
check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
"NV2", 2, 2);
read_feat_sel2();
check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
"TRF", 1, 1);

1
include/arch/aarch64/arch.h
View file

@ -119,6 +119,7 @@
#define MPAMVPM7_EL2 S3_4_C10_C6_7
#define MPAMVPMV_EL2 S3_4_C10_C4_1
#define TRFCR_EL2 S3_4_C1_C2_1
#define VNCR_EL2 S3_4_C2_C2_0
#define PMSCR_EL2 S3_4_C9_C9_0
#define TFSR_EL2 S3_4_C5_C6_0
#define CONTEXTIDR_EL2 S3_4_C13_C0_1

18
include/arch/aarch64/arch_features.h
View file

@ -423,10 +423,22 @@ static inline bool is_feat_trf_supported(void)
* Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization
* Support)
*******************************************************************************/
static inline unsigned int get_armv8_4_feat_nv_support(void)
static inline unsigned int read_feat_nv_id_field(void)
{
return (((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_NV_SHIFT) &
ID_AA64MMFR2_EL1_NV_MASK));
return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV);
}
static inline bool is_feat_nv2_supported(void)
{
if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_DISABLED) {
return false;
}
if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_nv_id_field() >= ID_AA64MMFR2_EL1_NV2_SUPPORTED;
}
/*******************************************************************************

1
include/arch/aarch64/arch_helpers.h
View file

@ -573,6 +573,7 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
/* Armv8.4 FEAT_TRF Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
/* Armv8.5 MTE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)

4
include/lib/el3_runtime/aarch64/context.h
View file

@ -521,10 +521,6 @@ void el2_sysregs_context_restore_mte(el2_sysregs_t *regs);
void el2_sysregs_context_save_ras(el2_sysregs_t *regs);
void el2_sysregs_context_restore_ras(el2_sysregs_t *regs);
#endif /* RAS_EXTENSION */
#if CTX_INCLUDE_NEVE_REGS
void el2_sysregs_context_save_nv2(el2_sysregs_t *regs);
void el2_sysregs_context_restore_nv2(el2_sysregs_t *regs);
#endif /* CTX_INCLUDE_NEVE_REGS */
#endif /* CTX_INCLUDE_EL2_REGS */
#if CTX_INCLUDE_FPREGS

24
lib/el3_runtime/aarch64/context.S
View file

@ -21,10 +21,6 @@
.global el2_sysregs_context_save_ras
.global el2_sysregs_context_restore_ras
#endif /* RAS_EXTENSION */
#if CTX_INCLUDE_NEVE_REGS
.global el2_sysregs_context_save_nv2
.global el2_sysregs_context_restore_nv2
#endif /* CTX_INCLUDE_NEVE_REGS */
#endif /* CTX_INCLUDE_EL2_REGS */
.global el1_sysregs_context_save
@ -238,26 +234,6 @@ func el2_sysregs_context_restore_ras
endfunc el2_sysregs_context_restore_ras
#endif /* RAS_EXTENSION */
#if CTX_INCLUDE_NEVE_REGS
func el2_sysregs_context_save_nv2
/*
* VNCR_EL2 register is saved only when FEAT_NV2 is supported.
*/
mrs x16, vncr_el2
str x16, [x0, #CTX_VNCR_EL2]
ret
endfunc el2_sysregs_context_save_nv2
func el2_sysregs_context_restore_nv2
/*
* VNCR_EL2 register is restored only when FEAT_NV2 is supported.
*/
ldr x16, [x0, #CTX_VNCR_EL2]
msr vncr_el2, x16
ret
endfunc el2_sysregs_context_restore_nv2
#endif /* CTX_INCLUDE_NEVE_REGS */
#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------

16
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -970,9 +970,12 @@ void cm_el2_sysregs_context_save(uint32_t security_state)
#if RAS_EXTENSION
el2_sysregs_context_save_ras(el2_sysregs_ctx);
#endif
#if CTX_INCLUDE_NEVE_REGS
el2_sysregs_context_save_nv2(el2_sysregs_ctx);
#endif
if (is_feat_nv2_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2,
read_vncr_el2());
}
if (is_feat_trf_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2());
}
@ -1036,9 +1039,10 @@ void cm_el2_sysregs_context_restore(uint32_t security_state)
#if RAS_EXTENSION
el2_sysregs_context_restore_ras(el2_sysregs_ctx);
#endif
#if CTX_INCLUDE_NEVE_REGS
el2_sysregs_context_restore_nv2(el2_sysregs_ctx);
#endif
if (is_feat_nv2_supported()) {
write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2));
}
if (is_feat_trf_supported()) {
write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2));
}

1
plat/arm/board/fvp/platform.mk
View file

@ -470,6 +470,7 @@ ENABLE_FEAT_FGT := 2
ENABLE_FEAT_HCX := 2
ENABLE_FEAT_TCR2 := 2
CTX_INCLUDE_NEVE_REGS := 2
ENABLE_FEAT_CSV2_2 := 2
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_PAN := 2