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fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset

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The model has a bug where it will not clear CPUPWRCTLR_EL1 on reset,
even though the actual cores do. The write of 1 to the bit itself
triggers the powerdown sequnece, regardless of the value before the
write. As such, the bug does not impact functionality but it does throw
off software reading it.

Clear the bit on Travis and Gelas as they are the only ones to require
reading it back.

Change-Id: I765a7fa055733d522480be30d412e3b417af2bd7
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This commit is contained in:
Boyan Karatotev 2024-10-16 11:36:29 +01:00
parent db5fe4f493
commit c9f352c362
2 changed files with 6 additions and 0 deletions
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3
lib/cpus/aarch64/cortex_gelas.S
View file

@ -35,6 +35,9 @@ cpu_reset_func_start cortex_gelas
* ----------------------------------------------------
*/
msr SSBS, xzr
/* model bug: not cleared on reset */
sysreg_bit_clear CORTEX_GELAS_CPUPWRCTLR_EL1, \
CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
cpu_reset_func_end cortex_gelas
/* ----------------------------------------------------

3
lib/cpus/aarch64/travis.S
View file

@ -35,6 +35,9 @@ cpu_reset_func_start travis
* ----------------------------------------------------
*/
msr SSBS, xzr
/* model bug: not cleared on reset */
sysreg_bit_clear TRAVIS_IMP_CPUPWRCTLR_EL1, \
TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
cpu_reset_func_end travis
func travis_core_pwr_dwn