From c9f352c362a8d114a055bb9206c5b6391ec3b96a Mon Sep 17 00:00:00 2001 From: Boyan Karatotev Date: Wed, 16 Oct 2024 11:36:29 +0100 Subject: [PATCH] fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset The model has a bug where it will not clear CPUPWRCTLR_EL1 on reset, even though the actual cores do. The write of 1 to the bit itself triggers the powerdown sequnece, regardless of the value before the write. As such, the bug does not impact functionality but it does throw off software reading it. Clear the bit on Travis and Gelas as they are the only ones to require reading it back. Change-Id: I765a7fa055733d522480be30d412e3b417af2bd7 Signed-off-by: Boyan Karatotev --- lib/cpus/aarch64/cortex_gelas.S | 3 +++ lib/cpus/aarch64/travis.S | 3 +++ 2 files changed, 6 insertions(+) diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S index e95820547..709bb129b 100644 --- a/lib/cpus/aarch64/cortex_gelas.S +++ b/lib/cpus/aarch64/cortex_gelas.S @@ -35,6 +35,9 @@ cpu_reset_func_start cortex_gelas * ---------------------------------------------------- */ msr SSBS, xzr + /* model bug: not cleared on reset */ + sysreg_bit_clear CORTEX_GELAS_CPUPWRCTLR_EL1, \ + CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT cpu_reset_func_end cortex_gelas /* ---------------------------------------------------- diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S index 246159a10..2e41668f4 100644 --- a/lib/cpus/aarch64/travis.S +++ b/lib/cpus/aarch64/travis.S @@ -35,6 +35,9 @@ cpu_reset_func_start travis * ---------------------------------------------------- */ msr SSBS, xzr + /* model bug: not cleared on reset */ + sysreg_bit_clear TRAVIS_IMP_CPUPWRCTLR_EL1, \ + TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT cpu_reset_func_end travis func travis_core_pwr_dwn