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Merge "feat(imx8m): obtain boot image set for imx8mn/mp" into integration
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commit
c9f05a326f
3 changed files with 84 additions and 2 deletions
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@ -17,6 +17,15 @@
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#include <lib/mmio.h>
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#include <sci/sci.h>
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#if defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
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/*
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* Defined in
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* table 11. ROM event log buffer address location
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* AN12853 "i.MX ROMs Log Events"
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*/
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#define ROM_LOG_BUFFER_ADDR 0x9E0
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#endif
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#if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
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#ifdef PLAT_imx8qm
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@ -177,6 +186,76 @@ int imx_src_handler(uint32_t smc_fid,
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}
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#endif /* defined(PLAT_imx8mm) || defined(PLAT_imx8mq) */
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#if defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
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static bool is_secondary_boot(void)
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{
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uint32_t *rom_log_addr = (uint32_t *)ROM_LOG_BUFFER_ADDR;
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bool is_secondary = false;
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uint32_t *rom_log;
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uint8_t event_id;
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/* If the ROM event log pointer is not valid. */
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if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xB00000 ||
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*rom_log_addr & 0x3) {
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return false;
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}
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/* Parse the ROM event ID version 2 log */
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rom_log = (uint32_t *)(uintptr_t)(*rom_log_addr);
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for (size_t i = 0; i < 128; i++) {
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event_id = rom_log[i] >> 24;
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switch (event_id) {
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case 0x00: /* End of list */
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return is_secondary;
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/* Log entries with 1 parameter, skip 1 */
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case 0x80: /* Perform the device initialization */
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case 0x81: /* The boot device initialization completes */
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case 0x82: /* Execute boot device driver pre-config */
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case 0x8F: /* The boot device initialization fails */
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case 0x90: /* Start to read data from boot device */
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case 0x91: /* Reading data from boot device completes */
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case 0x9F: /* Reading data from boot device fails */
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i += 1;
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continue;
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/* Log entries with 2 parameters, skip 2 */
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case 0xA0: /* Image authentication result */
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case 0xC0: /* Jump to the boot image soon */
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i += 2;
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continue;
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/* Booted the primary boot image */
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case 0x50:
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is_secondary = false;
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continue;
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/* Booted the secondary boot image */
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case 0x51:
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is_secondary = true;
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continue;
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}
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}
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return is_secondary;
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}
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int imx_src_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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void *handle)
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{
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switch (x1) {
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case IMX_SIP_SRC_SET_SECONDARY_BOOT:
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/* we do support that on these SoCs */
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break;
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case IMX_SIP_SRC_IS_SECONDARY_BOOT:
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return is_secondary_boot();
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default:
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return SMC_UNK;
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};
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return 0;
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}
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#endif /* defined(PLAT_imx8mn) || defined(PLAT_imx8mp) */
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static uint64_t imx_get_commit_hash(u_register_t x2,
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u_register_t x3,
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u_register_t x4)
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@ -60,7 +60,8 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid,
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case IMX_SIP_MISC_SET_TEMP:
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SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4));
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#endif
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) || defined(PLAT_imx8mn) || \
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defined(PLAT_imx8mp)
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case IMX_SIP_SRC:
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SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle));
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break;
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@ -68,7 +68,9 @@ int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3);
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#endif
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
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#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) || defined(PLAT_imx8mn) || \
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defined(PLAT_imx8mp)
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int imx_src_handler(uint32_t smc_fid, u_register_t x1,
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u_register_t x2, u_register_t x3, void *handle);
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#endif
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