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https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
refactor(st-bsec): improve BSEC driver
In order to ease the introduction of a new BSEC3 driver for STM32MP25, the BSEC2 driver is reworked. Unused functions are removed. The bsec_base global variable is removed in favor of the macro BSEC_BASE. A rework is also done around function checking the state of BSEC. Change-Id: I1ad76cb67333ab9a8fa1d65db34d74a712bf1190 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Patrick Delaunay
Yann Gautier
parent
b8816d3cbd
commit
c706104507
4 changed files with 136 additions and 324 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
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* Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -21,15 +21,26 @@
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#define BSEC_IP_VERSION_2_0 U(0x20)
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#define BSEC_IP_ID_2 U(0x100032)
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/*
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* IP configuration
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*/
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#define BSEC_OTP_MASK GENMASK(4, 0)
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#define BSEC_OTP_BANK_SHIFT 5
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#define BSEC_TIMEOUT_VALUE U(0xFFFF)
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#define OTP_ACCESS_SIZE (round_up(OTP_MAX_SIZE, __WORD_BIT) / __WORD_BIT)
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static uint32_t otp_nsec_access[OTP_ACCESS_SIZE] __unused;
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static uint32_t otp_nsec_access[OTP_ACCESS_SIZE] __maybe_unused;
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static uint32_t bsec_shadow_register(uint32_t otp);
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static uint32_t bsec_power_safmem(bool power);
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static uint32_t bsec_get_version(void);
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static uint32_t bsec_get_id(void);
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static uint32_t bsec_get_status(void);
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static uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value);
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/* BSEC access protection */
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static spinlock_t bsec_spinlock;
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static uintptr_t bsec_base;
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static void bsec_lock(void)
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{
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@ -47,7 +58,7 @@ static void bsec_unlock(void)
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static bool is_otp_invalid_mode(void)
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{
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bool ret = ((bsec_get_status() & BSEC_MODE_INVALID) == BSEC_MODE_INVALID);
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bool ret = ((bsec_get_status() & BSEC_OTP_STATUS_INVALID) == BSEC_OTP_STATUS_INVALID);
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if (ret) {
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ERROR("OTP mode is OTP-INVALID\n");
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@ -163,7 +174,7 @@ static void bsec_late_init(void)
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panic();
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}
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assert(bsec_base == bsec_info.base);
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assert(bsec_info.base == BSEC_BASE);
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bsec_dt_otp_nsec_access(fdt, node);
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}
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@ -177,6 +188,11 @@ static uint32_t otp_bank_offset(uint32_t otp)
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sizeof(uint32_t);
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}
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static uint32_t otp_bit_mask(uint32_t otp)
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{
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return BIT(otp & BSEC_OTP_MASK);
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}
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/*
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* bsec_check_error: check BSEC error status.
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* otp: OTP number.
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@ -186,10 +202,10 @@ static uint32_t otp_bank_offset(uint32_t otp)
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*/
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static uint32_t bsec_check_error(uint32_t otp, bool check_disturbed)
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{
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uint32_t bit = BIT(otp & BSEC_OTP_MASK);
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uint32_t bit = otp_bit_mask(otp);
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uint32_t bank = otp_bank_offset(otp);
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if ((mmio_read_32(bsec_base + BSEC_ERROR_OFF + bank) & bit) != 0U) {
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if ((mmio_read_32(BSEC_BASE + BSEC_ERROR_OFF + bank) & bit) != 0U) {
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return BSEC_ERROR;
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}
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@ -197,7 +213,7 @@ static uint32_t bsec_check_error(uint32_t otp, bool check_disturbed)
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return BSEC_OK;
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}
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if ((mmio_read_32(bsec_base + BSEC_DISTURBED_OFF + bank) & bit) != 0U) {
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if ((mmio_read_32(BSEC_BASE + BSEC_DISTURBED_OFF + bank) & bit) != 0U) {
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return BSEC_DISTURBED;
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}
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@ -210,14 +226,12 @@ static uint32_t bsec_check_error(uint32_t otp, bool check_disturbed)
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*/
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uint32_t bsec_probe(void)
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{
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bsec_base = BSEC_BASE;
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if (is_otp_invalid_mode()) {
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return BSEC_ERROR;
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}
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if ((((bsec_get_version() & BSEC_IPVR_MSK) != BSEC_IP_VERSION_1_1) &&
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((bsec_get_version() & BSEC_IPVR_MSK) != BSEC_IP_VERSION_2_0)) ||
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if (((bsec_get_version() != BSEC_IP_VERSION_1_1) &&
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(bsec_get_version() != BSEC_IP_VERSION_2_0)) ||
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(bsec_get_id() != BSEC_IP_ID_2)) {
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panic();
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}
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@ -228,103 +242,12 @@ uint32_t bsec_probe(void)
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return BSEC_OK;
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}
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/*
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* bsec_get_base: return BSEC base address.
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*/
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uint32_t bsec_get_base(void)
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{
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return bsec_base;
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}
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/*
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* bsec_set_config: enable and configure BSEC.
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* cfg: pointer to param structure used to set register.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_set_config(struct bsec_config *cfg)
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{
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uint32_t value;
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uint32_t result;
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if (is_otp_invalid_mode()) {
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return BSEC_ERROR;
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}
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value = ((((uint32_t)cfg->freq << BSEC_CONF_FRQ_SHIFT) &
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BSEC_CONF_FRQ_MASK) |
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(((uint32_t)cfg->pulse_width << BSEC_CONF_PRG_WIDTH_SHIFT) &
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BSEC_CONF_PRG_WIDTH_MASK) |
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(((uint32_t)cfg->tread << BSEC_CONF_TREAD_SHIFT) &
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BSEC_CONF_TREAD_MASK));
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, value);
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bsec_unlock();
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result = bsec_power_safmem((bool)cfg->power &
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BSEC_CONF_POWER_UP_MASK);
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if (result != BSEC_OK) {
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return result;
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}
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value = ((((uint32_t)cfg->upper_otp_lock << UPPER_OTP_LOCK_SHIFT) &
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UPPER_OTP_LOCK_MASK) |
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(((uint32_t)cfg->den_lock << DENREG_LOCK_SHIFT) &
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DENREG_LOCK_MASK) |
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(((uint32_t)cfg->prog_lock << GPLOCK_LOCK_SHIFT) &
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GPLOCK_LOCK_MASK));
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_LOCK_OFF, value);
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bsec_unlock();
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return BSEC_OK;
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}
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/*
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* bsec_get_config: return config parameters set in BSEC registers.
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* cfg: config param return.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_get_config(struct bsec_config *cfg)
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{
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uint32_t value;
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if (cfg == NULL) {
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return BSEC_INVALID_PARAM;
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}
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value = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF);
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cfg->power = (uint8_t)((value & BSEC_CONF_POWER_UP_MASK) >>
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BSEC_CONF_POWER_UP_SHIFT);
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cfg->freq = (uint8_t)((value & BSEC_CONF_FRQ_MASK) >>
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BSEC_CONF_FRQ_SHIFT);
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cfg->pulse_width = (uint8_t)((value & BSEC_CONF_PRG_WIDTH_MASK) >>
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BSEC_CONF_PRG_WIDTH_SHIFT);
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cfg->tread = (uint8_t)((value & BSEC_CONF_TREAD_MASK) >>
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BSEC_CONF_TREAD_SHIFT);
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value = mmio_read_32(bsec_base + BSEC_OTP_LOCK_OFF);
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cfg->upper_otp_lock = (uint8_t)((value & UPPER_OTP_LOCK_MASK) >>
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UPPER_OTP_LOCK_SHIFT);
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cfg->den_lock = (uint8_t)((value & DENREG_LOCK_MASK) >>
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DENREG_LOCK_SHIFT);
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cfg->prog_lock = (uint8_t)((value & GPLOCK_LOCK_MASK) >>
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GPLOCK_LOCK_SHIFT);
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return BSEC_OK;
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}
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/*
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* bsec_shadow_register: copy SAFMEM OTP to BSEC data.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_shadow_register(uint32_t otp)
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static uint32_t bsec_shadow_register(uint32_t otp)
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{
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uint32_t result;
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bool value;
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@ -345,7 +268,7 @@ uint32_t bsec_shadow_register(uint32_t otp)
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otp);
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}
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if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) {
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if ((bsec_get_status() & BSEC_OTP_STATUS_PWRON) == 0U) {
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result = bsec_power_safmem(true);
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if (result != BSEC_OK) {
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@ -357,9 +280,9 @@ uint32_t bsec_shadow_register(uint32_t otp)
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, otp | BSEC_READ);
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mmio_write_32(BSEC_BASE + BSEC_OTP_CTRL_OFF, otp | BSEC_READ);
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while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) {
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while ((bsec_get_status() & BSEC_OTP_STATUS_BUSY) != 0U) {
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;
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}
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@ -392,7 +315,7 @@ uint32_t bsec_read_otp(uint32_t *val, uint32_t otp)
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return BSEC_INVALID_PARAM;
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}
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*val = mmio_read_32(bsec_base + BSEC_OTP_DATA_OFF +
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*val = mmio_read_32(BSEC_BASE + BSEC_OTP_DATA_OFF +
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(otp * sizeof(uint32_t)));
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return BSEC_OK;
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@ -427,7 +350,7 @@ uint32_t bsec_write_otp(uint32_t val, uint32_t otp)
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/* Ensure integrity of each register access sequence */
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_DATA_OFF +
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mmio_write_32(BSEC_BASE + BSEC_OTP_DATA_OFF +
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(otp * sizeof(uint32_t)), val);
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bsec_unlock();
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@ -470,12 +393,11 @@ uint32_t bsec_program_otp(uint32_t val, uint32_t otp)
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return BSEC_PROG_FAIL;
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}
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if ((mmio_read_32(bsec_base + BSEC_OTP_LOCK_OFF) &
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BIT(BSEC_LOCK_PROGRAM)) != 0U) {
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if ((mmio_read_32(BSEC_BASE + BSEC_OTP_LOCK_OFF) & GPLOCK_LOCK_MASK) != 0U) {
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WARN("BSEC: GPLOCK activated, prog will be ignored\n");
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}
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if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) {
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if ((bsec_get_status() & BSEC_OTP_STATUS_PWRON) == 0U) {
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result = bsec_power_safmem(true);
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if (result != BSEC_OK) {
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@ -487,15 +409,15 @@ uint32_t bsec_program_otp(uint32_t val, uint32_t otp)
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_WRDATA_OFF, val);
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mmio_write_32(BSEC_BASE + BSEC_OTP_WRDATA_OFF, val);
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mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, otp | BSEC_WRITE);
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mmio_write_32(BSEC_BASE + BSEC_OTP_CTRL_OFF, otp | BSEC_WRITE);
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while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) {
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while ((bsec_get_status() & BSEC_OTP_STATUS_BUSY) != 0U) {
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;
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}
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if ((bsec_get_status() & BSEC_MODE_PROGFAIL_MASK) != 0U) {
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if ((bsec_get_status() & BSEC_OTP_STATUS_PROGFAIL) != 0U) {
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result = BSEC_PROG_FAIL;
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} else {
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result = bsec_check_error(otp, true);
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@ -517,6 +439,7 @@ uint32_t bsec_program_otp(uint32_t val, uint32_t otp)
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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#if defined(IMAGE_BL32)
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uint32_t bsec_permanent_lock_otp(uint32_t otp)
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{
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uint32_t result;
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@ -532,7 +455,7 @@ uint32_t bsec_permanent_lock_otp(uint32_t otp)
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return BSEC_INVALID_PARAM;
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}
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if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) {
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if ((bsec_get_status() & BSEC_OTP_STATUS_PWRON) == 0U) {
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result = bsec_power_safmem(true);
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if (result != BSEC_OK) {
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@ -554,16 +477,16 @@ uint32_t bsec_permanent_lock_otp(uint32_t otp)
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_OTP_WRDATA_OFF, data);
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mmio_write_32(BSEC_BASE + BSEC_OTP_WRDATA_OFF, data);
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mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF,
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mmio_write_32(BSEC_BASE + BSEC_OTP_CTRL_OFF,
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addr | BSEC_WRITE | BSEC_LOCK);
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while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) {
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while ((bsec_get_status() & BSEC_OTP_STATUS_BUSY) != 0U) {
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;
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}
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if ((bsec_get_status() & BSEC_MODE_PROGFAIL_MASK) != 0U) {
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if ((bsec_get_status() & BSEC_OTP_STATUS_PROGFAIL) != 0U) {
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result = BSEC_PROG_FAIL;
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} else {
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result = bsec_check_error(otp, false);
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@ -579,30 +502,14 @@ uint32_t bsec_permanent_lock_otp(uint32_t otp)
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return result;
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}
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/*
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* bsec_write_debug_conf: write value in debug feature.
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* to enable/disable debug service.
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* val: value to write.
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* return value: none.
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*/
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void bsec_write_debug_conf(uint32_t val)
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{
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if (is_otp_invalid_mode()) {
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return;
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}
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_DEN_OFF, val & BSEC_DEN_ALL_MSK);
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bsec_unlock();
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}
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#endif
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/*
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* bsec_read_debug_conf: return debug configuration register value.
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*/
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uint32_t bsec_read_debug_conf(void)
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{
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return mmio_read_32(bsec_base + BSEC_DEN_OFF);
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return mmio_read_32(BSEC_BASE + BSEC_DEN_OFF);
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}
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/*
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@ -618,59 +525,35 @@ void bsec_write_scratch(uint32_t val)
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}
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bsec_lock();
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mmio_write_32(bsec_base + BSEC_SCRATCH_OFF, val);
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mmio_write_32(BSEC_BASE + BSEC_SCRATCH_OFF, val);
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bsec_unlock();
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#else
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mmio_write_32(BSEC_BASE + BSEC_SCRATCH_OFF, val);
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#endif
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}
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/*
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* bsec_read_scratch: return scratch register value.
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*/
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uint32_t bsec_read_scratch(void)
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{
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return mmio_read_32(bsec_base + BSEC_SCRATCH_OFF);
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}
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/*
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* bsec_get_status: return status register value.
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*/
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uint32_t bsec_get_status(void)
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static uint32_t bsec_get_status(void)
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{
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return mmio_read_32(bsec_base + BSEC_OTP_STATUS_OFF);
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}
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/*
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* bsec_get_hw_conf: return hardware configuration register value.
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*/
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uint32_t bsec_get_hw_conf(void)
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{
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return mmio_read_32(bsec_base + BSEC_IPHW_CFG_OFF);
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return mmio_read_32(BSEC_BASE + BSEC_OTP_STATUS_OFF);
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}
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/*
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* bsec_get_version: return BSEC version register value.
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*/
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uint32_t bsec_get_version(void)
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static uint32_t bsec_get_version(void)
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{
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return mmio_read_32(bsec_base + BSEC_IPVR_OFF);
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return mmio_read_32(BSEC_BASE + BSEC_IPVR_OFF) & BSEC_IPVR_MSK;
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}
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/*
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* bsec_get_id: return BSEC ID register value.
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*/
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uint32_t bsec_get_id(void)
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static uint32_t bsec_get_id(void)
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{
|
||||
return mmio_read_32(bsec_base + BSEC_IP_ID_OFF);
|
||||
}
|
||||
|
||||
/*
|
||||
* bsec_get_magic_id: return BSEC magic number register value.
|
||||
*/
|
||||
uint32_t bsec_get_magic_id(void)
|
||||
{
|
||||
return mmio_read_32(bsec_base + BSEC_IP_MAGIC_ID_OFF);
|
||||
return mmio_read_32(BSEC_BASE + BSEC_IP_ID_OFF);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -681,7 +564,7 @@ uint32_t bsec_get_magic_id(void)
|
|||
uint32_t bsec_set_sr_lock(uint32_t otp)
|
||||
{
|
||||
uint32_t bank = otp_bank_offset(otp);
|
||||
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||||
uint32_t otp_mask = otp_bit_mask(otp);
|
||||
|
||||
if (is_otp_invalid_mode()) {
|
||||
return BSEC_ERROR;
|
||||
|
|
@ -692,7 +575,7 @@ uint32_t bsec_set_sr_lock(uint32_t otp)
|
|||
}
|
||||
|
||||
bsec_lock();
|
||||
mmio_write_32(bsec_base + BSEC_SRLOCK_OFF + bank, otp_mask);
|
||||
mmio_write_32(BSEC_BASE + BSEC_SRLOCK_OFF + bank, otp_mask);
|
||||
bsec_unlock();
|
||||
|
||||
return BSEC_OK;
|
||||
|
|
@ -707,14 +590,14 @@ uint32_t bsec_set_sr_lock(uint32_t otp)
|
|||
uint32_t bsec_read_sr_lock(uint32_t otp, bool *value)
|
||||
{
|
||||
uint32_t bank = otp_bank_offset(otp);
|
||||
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||||
uint32_t otp_mask = otp_bit_mask(otp);
|
||||
uint32_t bank_value;
|
||||
|
||||
if (otp > STM32MP1_OTP_MAX_ID) {
|
||||
return BSEC_INVALID_PARAM;
|
||||
}
|
||||
|
||||
bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank);
|
||||
bank_value = mmio_read_32(BSEC_BASE + BSEC_SRLOCK_OFF + bank);
|
||||
|
||||
*value = ((bank_value & otp_mask) != 0U);
|
||||
|
||||
|
|
@ -729,7 +612,7 @@ uint32_t bsec_read_sr_lock(uint32_t otp, bool *value)
|
|||
uint32_t bsec_set_sw_lock(uint32_t otp)
|
||||
{
|
||||
uint32_t bank = otp_bank_offset(otp);
|
||||
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||||
uint32_t otp_mask = otp_bit_mask(otp);
|
||||
|
||||
if (is_otp_invalid_mode()) {
|
||||
return BSEC_ERROR;
|
||||
|
|
@ -740,7 +623,7 @@ uint32_t bsec_set_sw_lock(uint32_t otp)
|
|||
}
|
||||
|
||||
bsec_lock();
|
||||
mmio_write_32(bsec_base + BSEC_SWLOCK_OFF + bank, otp_mask);
|
||||
mmio_write_32(BSEC_BASE + BSEC_SWLOCK_OFF + bank, otp_mask);
|
||||
bsec_unlock();
|
||||
|
||||
return BSEC_OK;
|
||||
|
|
@ -762,7 +645,7 @@ uint32_t bsec_read_sw_lock(uint32_t otp, bool *value)
|
|||
return BSEC_INVALID_PARAM;
|
||||
}
|
||||
|
||||
bank_value = mmio_read_32(bsec_base + BSEC_SWLOCK_OFF + bank);
|
||||
bank_value = mmio_read_32(BSEC_BASE + BSEC_SWLOCK_OFF + bank);
|
||||
|
||||
*value = ((bank_value & otp_mask) != 0U);
|
||||
|
||||
|
|
@ -777,7 +660,7 @@ uint32_t bsec_read_sw_lock(uint32_t otp, bool *value)
|
|||
uint32_t bsec_set_sp_lock(uint32_t otp)
|
||||
{
|
||||
uint32_t bank = otp_bank_offset(otp);
|
||||
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||||
uint32_t otp_mask = otp_bit_mask(otp);
|
||||
|
||||
if (is_otp_invalid_mode()) {
|
||||
return BSEC_ERROR;
|
||||
|
|
@ -788,7 +671,7 @@ uint32_t bsec_set_sp_lock(uint32_t otp)
|
|||
}
|
||||
|
||||
bsec_lock();
|
||||
mmio_write_32(bsec_base + BSEC_SPLOCK_OFF + bank, otp_mask);
|
||||
mmio_write_32(BSEC_BASE + BSEC_SPLOCK_OFF + bank, otp_mask);
|
||||
bsec_unlock();
|
||||
|
||||
return BSEC_OK;
|
||||
|
|
@ -810,7 +693,7 @@ uint32_t bsec_read_sp_lock(uint32_t otp, bool *value)
|
|||
return BSEC_INVALID_PARAM;
|
||||
}
|
||||
|
||||
bank_value = mmio_read_32(bsec_base + BSEC_SPLOCK_OFF + bank);
|
||||
bank_value = mmio_read_32(BSEC_BASE + BSEC_SPLOCK_OFF + bank);
|
||||
|
||||
*value = ((bank_value & otp_mask) != 0U);
|
||||
|
||||
|
|
@ -823,53 +706,23 @@ uint32_t bsec_read_sp_lock(uint32_t otp, bool *value)
|
|||
* value: read value (true or false).
|
||||
* return value: BSEC_OK if no error.
|
||||
*/
|
||||
uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value)
|
||||
static uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value)
|
||||
{
|
||||
uint32_t bank = otp_bank_offset(otp);
|
||||
uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK);
|
||||
uint32_t otp_mask = otp_bit_mask(otp);
|
||||
uint32_t bank_value;
|
||||
|
||||
if (otp > STM32MP1_OTP_MAX_ID) {
|
||||
return BSEC_INVALID_PARAM;
|
||||
}
|
||||
|
||||
bank_value = mmio_read_32(bsec_base + BSEC_WRLOCK_OFF + bank);
|
||||
bank_value = mmio_read_32(BSEC_BASE + BSEC_WRLOCK_OFF + bank);
|
||||
|
||||
*value = ((bank_value & otp_mask) != 0U);
|
||||
|
||||
return BSEC_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* bsec_otp_lock: Lock Upper OTP or Global Programming or Debug Enable.
|
||||
* service: Service to lock, see header file.
|
||||
* return value: BSEC_OK if no error.
|
||||
*/
|
||||
uint32_t bsec_otp_lock(uint32_t service)
|
||||
{
|
||||
uintptr_t reg = bsec_base + BSEC_OTP_LOCK_OFF;
|
||||
|
||||
if (is_otp_invalid_mode()) {
|
||||
return BSEC_ERROR;
|
||||
}
|
||||
|
||||
switch (service) {
|
||||
case BSEC_LOCK_UPPER_OTP:
|
||||
mmio_write_32(reg, BIT(BSEC_LOCK_UPPER_OTP));
|
||||
break;
|
||||
case BSEC_LOCK_DEBUG:
|
||||
mmio_write_32(reg, BIT(BSEC_LOCK_DEBUG));
|
||||
break;
|
||||
case BSEC_LOCK_PROGRAM:
|
||||
mmio_write_32(reg, BIT(BSEC_LOCK_PROGRAM));
|
||||
break;
|
||||
default:
|
||||
return BSEC_INVALID_PARAM;
|
||||
}
|
||||
|
||||
return BSEC_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* bsec_power_safmem: Activate or deactivate SAFMEM power.
|
||||
* power: true to power up, false to power down.
|
||||
|
|
@ -882,7 +735,7 @@ static uint32_t bsec_power_safmem(bool power)
|
|||
|
||||
bsec_lock();
|
||||
|
||||
register_val = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF);
|
||||
register_val = mmio_read_32(BSEC_BASE + BSEC_OTP_CONF_OFF);
|
||||
|
||||
if (power) {
|
||||
register_val |= BSEC_CONF_POWER_UP_MASK;
|
||||
|
|
@ -890,15 +743,15 @@ static uint32_t bsec_power_safmem(bool power)
|
|||
register_val &= ~BSEC_CONF_POWER_UP_MASK;
|
||||
}
|
||||
|
||||
mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, register_val);
|
||||
mmio_write_32(BSEC_BASE + BSEC_OTP_CONF_OFF, register_val);
|
||||
|
||||
if (power) {
|
||||
while (((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) &&
|
||||
while (((bsec_get_status() & BSEC_OTP_STATUS_PWRON) == 0U) &&
|
||||
(timeout != 0U)) {
|
||||
timeout--;
|
||||
}
|
||||
} else {
|
||||
while (((bsec_get_status() & BSEC_MODE_PWR_MASK) != 0U) &&
|
||||
while (((bsec_get_status() & BSEC_OTP_STATUS_PWRON) != 0U) &&
|
||||
(timeout != 0U)) {
|
||||
timeout--;
|
||||
}
|
||||
|
|
@ -915,28 +768,29 @@ static uint32_t bsec_power_safmem(bool power)
|
|||
|
||||
/*
|
||||
* bsec_shadow_read_otp: Load OTP from SAFMEM and provide its value.
|
||||
* otp_value: read value.
|
||||
* word: OTP number.
|
||||
* val: read value.
|
||||
* otp: OTP number.
|
||||
* return value: BSEC_OK if no error.
|
||||
*/
|
||||
uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word)
|
||||
uint32_t bsec_shadow_read_otp(uint32_t *val, uint32_t otp)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
result = bsec_shadow_register(word);
|
||||
result = bsec_shadow_register(otp);
|
||||
if (result != BSEC_OK) {
|
||||
ERROR("BSEC: %u Shadowing Error %u\n", word, result);
|
||||
ERROR("BSEC: %u Shadowing Error %u\n", otp, result);
|
||||
return result;
|
||||
}
|
||||
|
||||
result = bsec_read_otp(otp_value, word);
|
||||
result = bsec_read_otp(val, otp);
|
||||
if (result != BSEC_OK) {
|
||||
ERROR("BSEC: %u Read Error %u\n", word, result);
|
||||
ERROR("BSEC: %u Read Error %u\n", otp, result);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#if defined(IMAGE_BL32)
|
||||
/*
|
||||
* bsec_check_nsec_access_rights: check non-secure access rights to target OTP.
|
||||
* otp: OTP number.
|
||||
|
|
@ -944,7 +798,6 @@ uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word)
|
|||
*/
|
||||
uint32_t bsec_check_nsec_access_rights(uint32_t otp)
|
||||
{
|
||||
#if defined(IMAGE_BL32)
|
||||
if (otp > STM32MP1_OTP_MAX_ID) {
|
||||
return BSEC_INVALID_PARAM;
|
||||
}
|
||||
|
|
@ -954,8 +807,33 @@ uint32_t bsec_check_nsec_access_rights(uint32_t otp)
|
|||
return BSEC_ERROR;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return BSEC_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
uint32_t bsec_get_secure_state(void)
|
||||
{
|
||||
uint32_t status = bsec_get_status();
|
||||
uint32_t result = BSEC_STATE_INVALID;
|
||||
uint32_t otp_enc_id __maybe_unused;
|
||||
uint32_t otp_bit_len __maybe_unused;
|
||||
int res __maybe_unused;
|
||||
|
||||
if ((status & BSEC_OTP_STATUS_INVALID) != 0U) {
|
||||
result = BSEC_STATE_INVALID;
|
||||
} else {
|
||||
if ((status & BSEC_OTP_STATUS_SECURE) != 0U) {
|
||||
if (stm32mp_is_closed_device()) {
|
||||
result = BSEC_STATE_SEC_CLOSED;
|
||||
} else {
|
||||
result = BSEC_STATE_SEC_OPEN;
|
||||
}
|
||||
} else {
|
||||
/* OTP modes OPEN1 and OPEN2 are not supported */
|
||||
result = BSEC_STATE_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -12,13 +12,6 @@
|
|||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/*
|
||||
* IP configuration
|
||||
*/
|
||||
#define BSEC_OTP_MASK GENMASK(4, 0)
|
||||
#define BSEC_OTP_BANK_SHIFT 5
|
||||
#define BSEC_TIMEOUT_VALUE 0xFFFF
|
||||
|
||||
/*
|
||||
* Return status
|
||||
*/
|
||||
|
|
@ -32,98 +25,49 @@
|
|||
#define BSEC_RETRY 0xFFFFFFF8U
|
||||
#define BSEC_NOT_SUPPORTED 0xFFFFFFF7U
|
||||
#define BSEC_WRITE_LOCKED 0xFFFFFFF6U
|
||||
#define BSEC_ERROR_INVALID_FVR 0xFFFFFFF5U
|
||||
|
||||
/*
|
||||
* OTP MODE
|
||||
* get BSEC global state: result for bsec_get_secure_state()
|
||||
* @state: global state
|
||||
* [1:0] BSEC state
|
||||
* 00b: Sec Open
|
||||
* 01b: Sec Closed
|
||||
* 11b: Invalid
|
||||
* [8]: Hardware Key set = 1b
|
||||
*/
|
||||
#define BSEC_MODE_OPEN1 0x00U
|
||||
#define BSEC_MODE_SECURED 0x01U
|
||||
#define BSEC_MODE_OPEN2 0x02U
|
||||
#define BSEC_MODE_INVALID 0x04U
|
||||
|
||||
/*
|
||||
* OTP Lock services definition.
|
||||
* Value must corresponding to the bit number in the register.
|
||||
* Special case: (bit number << 1) for BSEC3.
|
||||
*/
|
||||
#define BSEC_LOCK_UPPER_OTP 0x00
|
||||
#define BSEC_LOCK_GWLOCK 0x01
|
||||
#define BSEC_LOCK_DEBUG 0x02
|
||||
#define BSEC_LOCK_PROGRAM 0x03
|
||||
#define BSEC_LOCK_KVLOCK 0x04
|
||||
|
||||
/*
|
||||
* Values for struct bsec_config::freq
|
||||
*/
|
||||
#define FREQ_10_20_MHZ 0x0
|
||||
#define FREQ_20_30_MHZ 0x1
|
||||
#define FREQ_30_45_MHZ 0x2
|
||||
#define FREQ_45_67_MHZ 0x3
|
||||
|
||||
/*
|
||||
* Device info structure, providing device-specific functions and a means of
|
||||
* adding driver-specific state.
|
||||
*/
|
||||
struct bsec_config {
|
||||
uint8_t den_lock; /*
|
||||
* Debug enable sticky lock
|
||||
* 1 debug enable is locked until next reset
|
||||
*/
|
||||
|
||||
/* BSEC2 only */
|
||||
uint8_t tread; /* SAFMEM Reading current level default 0 */
|
||||
uint8_t pulse_width; /* SAFMEM Programming pulse width default 1 */
|
||||
uint8_t freq; /*
|
||||
* SAFMEM CLOCK see freq value define
|
||||
* default FREQ_45_67_MHZ
|
||||
*/
|
||||
uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */
|
||||
uint8_t prog_lock; /*
|
||||
* Programming Sticky lock
|
||||
* 1 programming is locked until next reset
|
||||
*/
|
||||
uint8_t upper_otp_lock; /*
|
||||
* Shadowing of upper OTP sticky lock
|
||||
* 1 shadowing of upper OTP is locked
|
||||
* until next reset
|
||||
*/
|
||||
};
|
||||
#define BSEC_STATE_SEC_OPEN U(0x0)
|
||||
#define BSEC_STATE_SEC_CLOSED U(0x1)
|
||||
#define BSEC_STATE_INVALID U(0x3)
|
||||
#define BSEC_STATE_MASK GENMASK_32(1, 0)
|
||||
|
||||
uint32_t bsec_probe(void);
|
||||
uint32_t bsec_get_base(void);
|
||||
|
||||
uint32_t bsec_set_config(struct bsec_config *cfg);
|
||||
uint32_t bsec_get_config(struct bsec_config *cfg);
|
||||
|
||||
uint32_t bsec_shadow_register(uint32_t otp);
|
||||
uint32_t bsec_read_otp(uint32_t *val, uint32_t otp);
|
||||
uint32_t bsec_shadow_read_otp(uint32_t *val, uint32_t otp);
|
||||
uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
|
||||
uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
|
||||
uint32_t bsec_permanent_lock_otp(uint32_t otp);
|
||||
|
||||
void bsec_write_debug_conf(uint32_t val);
|
||||
uint32_t bsec_read_debug_conf(void);
|
||||
|
||||
void bsec_write_scratch(uint32_t val);
|
||||
uint32_t bsec_read_scratch(void);
|
||||
|
||||
uint32_t bsec_get_status(void);
|
||||
uint32_t bsec_get_hw_conf(void);
|
||||
uint32_t bsec_get_version(void);
|
||||
uint32_t bsec_get_id(void);
|
||||
uint32_t bsec_get_magic_id(void);
|
||||
|
||||
/* Sticky lock support */
|
||||
uint32_t bsec_set_sr_lock(uint32_t otp);
|
||||
uint32_t bsec_read_sr_lock(uint32_t otp, bool *value);
|
||||
uint32_t bsec_set_sw_lock(uint32_t otp);
|
||||
uint32_t bsec_read_sw_lock(uint32_t otp, bool *value);
|
||||
uint32_t bsec_set_sp_lock(uint32_t otp);
|
||||
uint32_t bsec_read_sp_lock(uint32_t otp, bool *value);
|
||||
uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value);
|
||||
uint32_t bsec_otp_lock(uint32_t service);
|
||||
|
||||
uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word);
|
||||
uint32_t bsec_get_secure_state(void);
|
||||
static inline bool bsec_mode_is_closed_device(void)
|
||||
{
|
||||
return (bsec_get_secure_state() & BSEC_STATE_MASK) == BSEC_STATE_SEC_CLOSED;
|
||||
}
|
||||
|
||||
#if defined(IMAGE_BL32)
|
||||
uint32_t bsec_permanent_lock_otp(uint32_t otp);
|
||||
uint32_t bsec_check_nsec_access_rights(uint32_t otp);
|
||||
#endif
|
||||
|
||||
#endif /* BSEC_H */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2022-2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -80,22 +80,17 @@
|
|||
#define GPLOCK_LOCK_SHIFT 4
|
||||
|
||||
/* BSEC_OTP_STATUS Register */
|
||||
#define BSEC_MODE_STATUS_MASK GENMASK(2, 0)
|
||||
#define BSEC_MODE_SECURE_MASK BIT(0)
|
||||
#define BSEC_MODE_FULLDBG_MASK BIT(1)
|
||||
#define BSEC_MODE_INVALID_MASK BIT(2)
|
||||
#define BSEC_MODE_BUSY_MASK BIT(3)
|
||||
#define BSEC_MODE_PROGFAIL_MASK BIT(4)
|
||||
#define BSEC_MODE_PWR_MASK BIT(5)
|
||||
#define BSEC_MODE_BIST1_LOCK_MASK BIT(6)
|
||||
#define BSEC_MODE_BIST2_LOCK_MASK BIT(7)
|
||||
#define BSEC_OTP_STATUS_SECURE BIT(0)
|
||||
#define BSEC_OTP_STATUS_INVALID BIT(2)
|
||||
#define BSEC_OTP_STATUS_BUSY BIT(3)
|
||||
#define BSEC_OTP_STATUS_PROGFAIL BIT(4)
|
||||
#define BSEC_OTP_STATUS_PWRON BIT(5)
|
||||
|
||||
/* BSEC_DENABLE Register */
|
||||
#define BSEC_HDPEN BIT(4)
|
||||
#define BSEC_SPIDEN BIT(5)
|
||||
#define BSEC_SPINDEN BIT(6)
|
||||
#define BSEC_DBGSWGEN BIT(10)
|
||||
#define BSEC_DEN_ALL_MSK GENMASK(10, 0)
|
||||
|
||||
/* BSEC_FENABLE Register */
|
||||
#define BSEC_FEN_ALL_MSK GENMASK(14, 0)
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2022, STMicroelectronics - All Rights Reserved
|
||||
* Copyright (c) 2016-2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/st/bsec.h>
|
||||
#include <drivers/st/bsec2_reg.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <stm32mp1_smc.h>
|
||||
|
||||
#include "bsec_svc.h"
|
||||
|
|
@ -39,12 +39,7 @@ uint32_t bsec_main(uint32_t x1, uint32_t x2, uint32_t x3,
|
|||
break;
|
||||
}
|
||||
|
||||
result = bsec_shadow_register(x2);
|
||||
if (result != BSEC_OK) {
|
||||
break;
|
||||
}
|
||||
|
||||
result = bsec_read_otp(ret_otp_value, x2);
|
||||
result = bsec_shadow_read_otp(ret_otp_value, x2);
|
||||
if (result != BSEC_OK) {
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue