mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00
feat(rde1edge): remove support for RD-E1-Edge
As RD-E1_Edge is no longer actively supported and has been in the deprecated list for a while, remove its support. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: Iff66ad498dd99e44e2e6b79251ba2cbefbd5f3eb
This commit is contained in:
Rohit Mathew
Omkar Anand Kulkarni
parent
10dcffedb3
commit
c69253cc3a
12 changed files with 2 additions and 343 deletions
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@ -525,7 +525,6 @@ Arm Reference Design platform ports
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:|M|: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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:|M|: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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:|G|: `vijayenthiran-arm`_
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:|G|: `vijayenthiran-arm`_
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:|F|: plat/arm/css/sgi/
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:|F|: plat/arm/css/sgi/
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:|F|: plat/arm/board/rde1edge/
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:|F|: plat/arm/board/rdn1edge/
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:|F|: plat/arm/board/rdn1edge/
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:|F|: plat/arm/board/rdn2/
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:|F|: plat/arm/board/rdn2/
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:|F|: plat/arm/board/rdv1/
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:|F|: plat/arm/board/rdv1/
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@ -59,7 +59,6 @@ documentation associated with them.
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- Arm Neoverse N1 System Development Platform (N1SDP)
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- Arm Neoverse N1 System Development Platform (N1SDP)
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- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
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- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
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- Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
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- Arm SGI-575
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- Arm SGI-575
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- MediaTek MT8173 SoCs
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- MediaTek MT8173 SoCs
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@ -81,9 +80,9 @@ Deprecated platforms
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+----------------+----------------+--------------------+--------------------+
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+----------------+----------------+--------------------+--------------------+
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| tc1 | Arm | 2.10 | TBD |
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| tc1 | Arm | 2.10 | TBD |
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+----------------+----------------+--------------------+--------------------+
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+----------------+----------------+--------------------+--------------------+
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| rde1edge | Arm | 2.9 | 3.0 |
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| rde1edge | Arm | 2.9 | 2.11 |
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+----------------+----------------+--------------------+--------------------+
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+----------------+----------------+--------------------+--------------------+
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--------------
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--------------
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*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
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*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
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@ -1,27 +0,0 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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tb_fw-config {
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load-address = <0x0 0x4001300>;
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max-size = <0x200>;
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id = <TB_FW_CONFIG_ID>;
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};
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nt_fw-config {
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load-address = <0x0 0xFEF00000>;
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max-size = <0x0100000>;
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id = <NT_FW_CONFIG_ID>;
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};
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};
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};
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@ -1,23 +0,0 @@
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/*
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* Copyright (c) 2018-2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* compatible string */
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compatible = "arm,rd-e1edge";
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/*
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* Place holder for system-id node with default values. The
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* value of platform-id and config-id will be set to the
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* correct values during the BL2 stage of boot.
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*/
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system-id {
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platform-id = <0x0>;
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config-id = <0x0>;
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multi-chip-mode = <0x0>;
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};
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};
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@ -1,28 +0,0 @@
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/*
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* Copyright (c) 2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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tb_fw-config {
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compatible = "arm,tb_fw";
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/* Disable authentication for development */
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disable_auth = <0x0>;
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/*
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* The following two entries are placeholders for Mbed TLS
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* heap information. The default values don't matter since
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* they will be overwritten by BL1.
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* In case of having shared Mbed TLS heap between BL1 and BL2,
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* BL1 will populate these two properties with the respective
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* info about the shared heap. This info will be available for
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* BL2 in order to locate and re-use the heap.
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*/
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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};
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@ -1,48 +0,0 @@
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/*
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* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <sgi_sdei.h>
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#include <sgi_soc_platform_def.h>
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#define PLAT_ARM_CLUSTER_COUNT U(2)
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8)
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#define CSS_SGI_MAX_PE_PER_CPU U(2)
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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/* Base address of DMC-620 instances */
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#define RDE1EDGE_DMC620_BASE0 UL(0x4e000000)
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#define RDE1EDGE_DMC620_BASE1 UL(0x4e100000)
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3
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/* Maximum number of address bits used per chip */
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#define CSS_SGI_ADDR_BITS_PER_CHIP U(36)
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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#define PLAT_ARM_GICR_BASE UL(0x300C0000)
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#endif /* PLATFORM_DEF_H */
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@ -1,69 +0,0 @@
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#
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# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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$(warning Platform ${PLAT} is deprecated. \
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Some of the features might not work as expected)
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include plat/arm/css/sgi/sgi-common.mk
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RDE1EDGE_BASE = plat/arm/board/rde1edge
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PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/
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SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
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PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
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BL1_SOURCES += ${SGI_CPU_SOURCES} \
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${RDE1EDGE_BASE}/rde1edge_err.c
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BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \
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${RDE1EDGE_BASE}/rde1edge_security.c \
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${RDE1EDGE_BASE}/rde1edge_err.c \
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drivers/arm/tzc/tzc_dmc620.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${SGI_CPU_SOURCES} \
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${RDE1EDGE_BASE}/rde1edge_plat.c \
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${RDE1EDGE_BASE}/rde1edge_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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ifeq (${TRUSTED_BOARD_BOOT}, 1)
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BL1_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
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BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
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endif
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \
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${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
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FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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# Add the FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
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FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
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NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
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# Add the NT_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
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ifneq ($(CSS_SGI_CHIP_COUNT),1)
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$(error "Chip count for RDE1Edge should be 1, currently set to \
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${CSS_SGI_CHIP_COUNT}.")
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endif
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ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
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$(error "CSS_SGI_PLATFORM_VARIANT for RD-E1-Edge should always be 0, \
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currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
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endif
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override CTX_INCLUDE_AARCH32_REGS := 0
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@ -1,17 +0,0 @@
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/*
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* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/*
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* rde1edge error handler
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*/
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void __dead2 plat_arm_error_handler(int err)
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{
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while (true) {
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wfi();
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}
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}
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@ -1,29 +0,0 @@
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/*
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* Copyright (c) 2018-2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/common/platform.h>
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#include <sgi_plat.h>
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unsigned int plat_arm_sgi_get_platform_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
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& SID_SYSTEM_ID_PART_NUM_MASK;
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}
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unsigned int plat_arm_sgi_get_config_id(void)
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{
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return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
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}
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unsigned int plat_arm_sgi_get_multi_chip_mode(void)
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{
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return 0;
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}
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void bl31_platform_setup(void)
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{
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sgi_bl31_common_platform_setup();
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}
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/*
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* Copyright (c) 2019-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/debug.h>
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#include <sgi_dmc620_tzc_regions.h>
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uintptr_t rde1edge_dmc_base[] = {
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RDE1EDGE_DMC620_BASE0,
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RDE1EDGE_DMC620_BASE1
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};
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static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
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.dmc_base = rde1edge_dmc_base,
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.dmc_count = ARRAY_SIZE(rde1edge_dmc_base)
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};
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static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
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CSS_SGI_DMC620_TZC_REGIONS_DEF
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};
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static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
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.plat_drv_data = &rde1edge_plat_driver_data,
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.plat_acc_addr_data = rde1edge_acc_addr_data,
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.acc_addr_count = ARRAY_SIZE(rde1edge_acc_addr_data)
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};
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/* Initialize the secure environment */
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void plat_arm_security_setup(void)
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{
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arm_tzc_dmc620_setup(&rde1edge_plat_config_data);
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}
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/*
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* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/******************************************************************************
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* The power domain tree descriptor. RD-E1-Edge platform consists of two
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* clusters with eight CPUs in each cluster. The CPUs are multi-threaded with
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* two threads per CPU.
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******************************************************************************/
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static const unsigned char rde1edge_pd_tree_desc[] = {
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CSS_SGI_CHIP_COUNT,
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PLAT_ARM_CLUSTER_COUNT,
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CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU,
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CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU
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};
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/******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return rde1edge_pd_tree_desc;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
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||||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
|
|
||||||
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
|
|
||||||
};
|
|
||||||
|
|
@ -1,26 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2020, Arm Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <plat/arm/common/plat_arm.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Return the ROTPK hash in the following ASN.1 structure in DER format:
|
|
||||||
*
|
|
||||||
* AlgorithmIdentifier ::= SEQUENCE {
|
|
||||||
* algorithm OBJECT IDENTIFIER,
|
|
||||||
* parameters ANY DEFINED BY algorithm OPTIONAL
|
|
||||||
* }
|
|
||||||
*
|
|
||||||
* DigestInfo ::= SEQUENCE {
|
|
||||||
* digestAlgorithm AlgorithmIdentifier,
|
|
||||||
* digest OCTET STRING
|
|
||||||
* }
|
|
||||||
*/
|
|
||||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
|
||||||
unsigned int *flags)
|
|
||||||
{
|
|
||||||
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
|
|
||||||
}
|
|
||||||
Loading…
Add table
Reference in a new issue