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1d74b4bbba
The value of the macro CSS_SGI_REMOTE_CHIP_MEM_OFFSET can be different across all the Neoverse reference design platforms. This value depends on the number of address bits used per chip. So let all platforms define CSS_SGI_ADDR_BITS_PER_CHIP which specifies the number of address bits used per chip. In addition to this, reuse the definition of CSS_SGI_ADDR_BITS_PER_CHIP for single chip platforms and CSS_SGI_REMOTE_CHIP_MEM_OFFSET for multi- chip platforms to determine the maximum address space size. Also, increase the RD-N2 multi-chip address space per chip from 4TB to 64TB. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: If5e69ec26c2389304c71911729d4addbdf8b2686
48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/*
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* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <sgi_sdei.h>
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#include <sgi_soc_platform_def.h>
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#define PLAT_ARM_CLUSTER_COUNT U(2)
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#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8)
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#define CSS_SGI_MAX_PE_PER_CPU U(2)
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#define PLAT_CSS_MHU_BASE UL(0x45400000)
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/* Base address of DMC-620 instances */
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#define RDE1EDGE_DMC620_BASE0 UL(0x4e000000)
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#define RDE1EDGE_DMC620_BASE1 UL(0x4e100000)
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3
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/* Maximum number of address bits used per chip */
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#define CSS_SGI_ADDR_BITS_PER_CHIP U(36)
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/*
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* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
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*/
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#ifdef __aarch64__
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
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#else
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#endif
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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#define PLAT_ARM_GICR_BASE UL(0x300C0000)
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#endif /* PLATFORM_DEF_H */
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