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feat(rde1edge): remove support for RD-E1-Edge

Browse source 
As RD-E1_Edge is no longer actively supported and has been in the
deprecated list for a while, remove its support.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Iff66ad498dd99e44e2e6b79251ba2cbefbd5f3eb
This commit is contained in:
Rohit Mathew 2024-01-11 15:55:11 +00:00 • committed by Omkar Anand Kulkarni
parent 10dcffedb3
commit c69253cc3a
12 changed files with 2 additions and 343 deletions
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1
docs/about/maintainers.rst
View file

@ -525,7 +525,6 @@ Arm Reference Design platform ports
:|M|: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
:|G|: `vijayenthiran-arm`_
:|F|: plat/arm/css/sgi/
:|F|: plat/arm/board/rde1edge/
:|F|: plat/arm/board/rdn1edge/
:|F|: plat/arm/board/rdn2/
:|F|: plat/arm/board/rdv1/

5
docs/plat/index.rst
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@ -59,7 +59,6 @@ documentation associated with them.
- Arm Neoverse N1 System Development Platform (N1SDP)
- Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
- Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
- Arm SGI-575
- MediaTek MT8173 SoCs
@ -81,9 +80,9 @@ Deprecated platforms
+----------------+----------------+--------------------+--------------------+
| tc1 | Arm | 2.10 | TBD |
+----------------+----------------+--------------------+--------------------+
| rde1edge | Arm | 2.9 | 3.0 |
| rde1edge | Arm | 2.9 | 2.11 |
+----------------+----------------+--------------------+--------------------+
--------------
*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*

27
plat/arm/board/rde1edge/fdts/rde1edge_fw_config.dts
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@ -1,27 +0,0 @@
/*
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
/dts-v1/;
/ {
dtb-registry {
compatible = "fconf,dyn_cfg-dtb_registry";
tb_fw-config {
load-address = <0x0 0x4001300>;
max-size = <0x200>;
id = <TB_FW_CONFIG_ID>;
};
nt_fw-config {
load-address = <0x0 0xFEF00000>;
max-size = <0x0100000>;
id = <NT_FW_CONFIG_ID>;
};
};
};

23
plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
View file

@ -1,23 +0,0 @@
/*
* Copyright (c) 2018-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
/* compatible string */
compatible = "arm,rd-e1edge";
/*
* Place holder for system-id node with default values. The
* value of platform-id and config-id will be set to the
* correct values during the BL2 stage of boot.
*/
system-id {
platform-id = <0x0>;
config-id = <0x0>;
multi-chip-mode = <0x0>;
};
};

28
plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
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@ -1,28 +0,0 @@
/*
* Copyright (c) 2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
tb_fw-config {
compatible = "arm,tb_fw";
/* Disable authentication for development */
disable_auth = <0x0>;
/*
* The following two entries are placeholders for Mbed TLS
* heap information. The default values don't matter since
* they will be overwritten by BL1.
* In case of having shared Mbed TLS heap between BL1 and BL2,
* BL1 will populate these two properties with the respective
* info about the shared heap. This info will be available for
* BL2 in order to locate and re-use the heap.
*/
mbedtls_heap_addr = <0x0 0x0>;
mbedtls_heap_size = <0x0>;
};
};

48
plat/arm/board/rde1edge/include/platform_def.h
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@ -1,48 +0,0 @@
/*
* Copyright (c) 2018-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
#include <sgi_sdei.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8)
#define CSS_SGI_MAX_PE_PER_CPU U(2)
#define PLAT_CSS_MHU_BASE UL(0x45400000)
/* Base address of DMC-620 instances */
#define RDE1EDGE_DMC620_BASE0 UL(0x4e000000)
#define RDE1EDGE_DMC620_BASE1 UL(0x4e100000)
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3
/* Maximum number of address bits used per chip */
#define CSS_SGI_ADDR_BITS_PER_CHIP U(36)
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#endif
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x300C0000)
#endif /* PLATFORM_DEF_H */

69
plat/arm/board/rde1edge/platform.mk
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@ -1,69 +0,0 @@
#
# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
$(warning Platform ${PLAT} is deprecated. \
Some of the features might not work as expected)
include plat/arm/css/sgi/sgi-common.mk
RDE1EDGE_BASE = plat/arm/board/rde1edge
PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDE1EDGE_BASE}/rde1edge_err.c
BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \
${RDE1EDGE_BASE}/rde1edge_security.c \
${RDE1EDGE_BASE}/rde1edge_err.c \
drivers/arm/tzc/tzc_dmc620.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
${RDE1EDGE_BASE}/rde1edge_plat.c \
${RDE1EDGE_BASE}/rde1edge_topology.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
ifeq (${TRUSTED_BOARD_BOOT}, 1)
BL1_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_trusted_boot.c
endif
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \
${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
ifneq ($(CSS_SGI_CHIP_COUNT),1)
$(error "Chip count for RDE1Edge should be 1, currently set to \
${CSS_SGI_CHIP_COUNT}.")
endif
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-E1-Edge should always be 0, \
currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
endif
override CTX_INCLUDE_AARCH32_REGS := 0

17
plat/arm/board/rde1edge/rde1edge_err.c
View file

@ -1,17 +0,0 @@
/*
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/*
* rde1edge error handler
*/
void __dead2 plat_arm_error_handler(int err)
{
while (true) {
wfi();
}
}

29
plat/arm/board/rde1edge/rde1edge_plat.c
View file

@ -1,29 +0,0 @@
/*
* Copyright (c) 2018-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/common/platform.h>
#include <sgi_plat.h>
unsigned int plat_arm_sgi_get_platform_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
& SID_SYSTEM_ID_PART_NUM_MASK;
}
unsigned int plat_arm_sgi_get_config_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
}
unsigned int plat_arm_sgi_get_multi_chip_mode(void)
{
return 0;
}
void bl31_platform_setup(void)
{
sgi_bl31_common_platform_setup();
}

36
plat/arm/board/rde1edge/rde1edge_security.c
View file

@ -1,36 +0,0 @@
/*
* Copyright (c) 2019-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <common/debug.h>
#include <sgi_dmc620_tzc_regions.h>
uintptr_t rde1edge_dmc_base[] = {
RDE1EDGE_DMC620_BASE0,
RDE1EDGE_DMC620_BASE1
};
static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
.dmc_base = rde1edge_dmc_base,
.dmc_count = ARRAY_SIZE(rde1edge_dmc_base)
};
static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
.plat_drv_data = &rde1edge_plat_driver_data,
.plat_acc_addr_data = rde1edge_acc_addr_data,
.acc_addr_count = ARRAY_SIZE(rde1edge_acc_addr_data)
};
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
arm_tzc_dmc620_setup(&rde1edge_plat_config_data);
}

36
plat/arm/board/rde1edge/rde1edge_topology.c
View file

@ -1,36 +0,0 @@
/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/******************************************************************************
* The power domain tree descriptor. RD-E1-Edge platform consists of two
* clusters with eight CPUs in each cluster. The CPUs are multi-threaded with
* two threads per CPU.
******************************************************************************/
static const unsigned char rde1edge_pd_tree_desc[] = {
CSS_SGI_CHIP_COUNT,
PLAT_ARM_CLUSTER_COUNT,
CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU,
CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU
};
/******************************************************************************
* This function returns the topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return rde1edge_pd_tree_desc;
}
/*******************************************************************************
* The array mapping platform core position (implemented by plat_my_core_pos())
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
};

26
plat/arm/board/rde1edge/rde1edge_trusted_boot.c
View file

@ -1,26 +0,0 @@
/*
* Copyright (c) 2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
/*
* Return the ROTPK hash in the following ASN.1 structure in DER format:
*
* AlgorithmIdentifier ::= SEQUENCE {
* algorithm OBJECT IDENTIFIER,
* parameters ANY DEFINED BY algorithm OPTIONAL
* }
*
* DigestInfo ::= SEQUENCE {
* digestAlgorithm AlgorithmIdentifier,
* digest OCTET STRING
* }
*/
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
unsigned int *flags)
{
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
}