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fix(errata): workaround for Cortex-A510 erratum 2172148
Cortex-A510 erratum 2172148 is a Cat B erratum that applies to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1. SDEN can be found here: https://developer.arm.com/documentation/SDEN2397239 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I1784d643ca3d1d448340cd421facb5f229df1d22
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@ -502,6 +502,10 @@ For Cortex-A510, the following errata build flags are defined :
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Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
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r0p3 and r1p0, it is fixed in r1p1.
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- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
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Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
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r0p3 and r1p0, it is fixed in r1p1.
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DSU Errata Workarounds
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----------------------
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@ -15,6 +15,8 @@
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#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
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#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
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#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
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#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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@ -230,6 +230,40 @@ func check_errata_2218950
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b cpu_rev_var_ls
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endfunc check_errata_2218950
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2172148.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0, and is fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2172148_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2172148
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cbz x0, 1f
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/*
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* Force L2 allocation of transient lines by setting
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* CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
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*/
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mrs x0, CORTEX_A510_CPUECTLR_EL1
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mov x1, #1
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
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msr CORTEX_A510_CPUECTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2172148_wa
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func check_errata_2172148
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/* Applies to r1p0 and lower */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2172148
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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@ -266,6 +300,7 @@ func cortex_a510_errata_report
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report_errata ERRATA_A510_2041909, cortex_a510, 2041909
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report_errata ERRATA_A510_2250311, cortex_a510, 2250311
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report_errata ERRATA_A510_2218950, cortex_a510, 2218950
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report_errata ERRATA_A510_2172148, cortex_a510, 2172148
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ldp x8, x30, [sp], #16
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ret
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@ -313,6 +348,11 @@ func cortex_a510_reset_func
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bl errata_cortex_a510_2218950_wa
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#endif
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#if ERRATA_A510_2172148
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mov x0, x18
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bl errata_cortex_a510_2172148_wa
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#endif
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ret x19
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endfunc cortex_a510_reset_func
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@ -556,6 +556,10 @@ ERRATA_A510_2250311 ?=0
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# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
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ERRATA_A510_2218950 ?=0
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# Flag to apply erratum 2172148 workaround during reset. This erratum applies
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# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
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ERRATA_A510_2172148 ?=0
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# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
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# Applying the workaround results in higher DSU power consumption on idle.
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ERRATA_DSU_798953 ?=0
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@ -1037,6 +1041,10 @@ $(eval $(call add_define,ERRATA_A510_2250311))
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$(eval $(call assert_boolean,ERRATA_A510_2218950))
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$(eval $(call add_define,ERRATA_A510_2218950))
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# Process ERRATA_A510_2172148 flag
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$(eval $(call assert_boolean,ERRATA_A510_2172148))
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$(eval $(call add_define,ERRATA_A510_2172148))
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# Process ERRATA_DSU_798953 flag
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$(eval $(call assert_boolean,ERRATA_DSU_798953))
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$(eval $(call add_define,ERRATA_DSU_798953))
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