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fix(errata): workaround for Cortex-A510 erratum 2218950

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Cortex-A510 erratum 2218950 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Icb6e369946f8978a08cf8ed5e4452782efb0a77a
This commit is contained in:
johpow01 2022-02-14 20:19:08 -06:00 • committed by John Powell
parent 7f304b02a8
commit cc79018b71
3 changed files with 55 additions and 0 deletions

4
docs/design/cpu-specific-build-macros.rst
View file

@ -498,6 +498,10 @@ For Cortex-A510, the following errata build flags are defined :
r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
ENABLE_MPMM=1.
- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
r0p3 and r1p0, it is fixed in r1p1.
DSU Errata Workarounds
----------------------

43
lib/cpus/aarch64/cortex_a510.S
View file

@ -193,6 +193,43 @@ func check_errata_2250311
b cpu_rev_var_ls
endfunc check_errata_2250311
/* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2218950.
* This applies only to revisions r0p0, r0p1, r0p2,
* r0p3 and r1p0, and is fixed in r1p1.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_cortex_a510_2218950_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2218950
cbz x0, 1f
/* Source register for BFI */
mov x1, #1
/* Set bit 18 in CPUACTLR_EL1 */
mrs x0, CORTEX_A510_CPUACTLR_EL1
bfi x0, x1, #18, #1
msr CORTEX_A510_CPUACTLR_EL1, x0
/* Set bit 25 in CMPXACTLR_EL1 */
mrs x0, CORTEX_A510_CMPXACTLR_EL1
bfi x0, x1, #25, #1
msr CORTEX_A510_CMPXACTLR_EL1, x0
1:
ret x17
endfunc errata_cortex_a510_2218950_wa
func check_errata_2218950
/* Applies to r1p0 and lower */
mov x1, #0x10
b cpu_rev_var_ls
endfunc check_errata_2218950
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
@ -228,6 +265,7 @@ func cortex_a510_errata_report
report_errata ERRATA_A510_2042739, cortex_a510, 2042739
report_errata ERRATA_A510_2041909, cortex_a510, 2041909
report_errata ERRATA_A510_2250311, cortex_a510, 2250311
report_errata ERRATA_A510_2218950, cortex_a510, 2218950
ldp x8, x30, [sp], #16
ret
@ -270,6 +308,11 @@ func cortex_a510_reset_func
bl errata_cortex_a510_2250311_wa
#endif
#if ERRATA_A510_2218950
mov x0, x18
bl errata_cortex_a510_2218950_wa
#endif
ret x19
endfunc cortex_a510_reset_func

8
lib/cpus/cpu-ops.mk
View file

@ -552,6 +552,10 @@ ERRATA_A510_2041909 ?=0
# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
ERRATA_A510_2250311 ?=0
# Flag to apply erratum 2218950 workaround during reset. This erratum applies
# to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
ERRATA_A510_2218950 ?=0
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@ -1029,6 +1033,10 @@ $(eval $(call add_define,ERRATA_A510_2041909))
$(eval $(call assert_boolean,ERRATA_A510_2250311))
$(eval $(call add_define,ERRATA_A510_2250311))
# Process ERRATA_A510_2218950 flag
$(eval $(call assert_boolean,ERRATA_A510_2218950))
$(eval $(call add_define,ERRATA_A510_2218950))
# Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))