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https://github.com/ARM-software/arm-trusted-firmware.git
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refactor(ti): move out k3/common to ti/common
This will allow us to support more platforms that share commonalities like the k3_gicv3, console, helpers, etc. With this new common folder location, we can move the previously created ti_bl31_setup file into the new location so it can be shared across multiple TI SoCs when need comes. With this, also update all copyright dates. Change-Id: Ie4365e32cd3b4b5870fe2cd03843400506e46265 Signed-off-by: Dhruva Gole <d-gole@ti.com>
This commit is contained in:
Dhruva Gole
parent
26605cdd7e
commit
bfac44b51b
12 changed files with 202 additions and 184 deletions
182
plat/ti/common/include/ti_platform_defs.h
Normal file
182
plat/ti/common/include/ti_platform_defs.h
Normal file
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@ -0,0 +1,182 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TI_PLATFORM_DEF_H
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#define TI_PLATFORM_DEF_H
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <board_def.h>
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stack */
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#if IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#define PLATFORM_SYSTEM_COUNT 1
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#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
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K3_CLUSTER1_CORE_COUNT + \
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K3_CLUSTER2_CORE_COUNT + \
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K3_CLUSTER3_CORE_COUNT)
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#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \
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(K3_CLUSTER1_CORE_COUNT != 0) + \
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(K3_CLUSTER2_CORE_COUNT != 0) + \
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(K3_CLUSTER3_CORE_COUNT != 0))
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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/*******************************************************************************
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* Memory layout constants
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******************************************************************************/
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/*
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* This RAM will be used for the bootloader including code, bss, and stacks.
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* It may need to be increased if BL31 grows in size.
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*
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* The link addresses are determined by BL31_BASE + offset.
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* When ENABLE_PIE is set, the TF images can be loaded anywhere, so
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* BL31_BASE is really arbitrary.
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*
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* When ENABLE_PIE is unset, BL31_BASE should be chosen so that
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* it matches to the physical address where BL31 is loaded, that is,
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* BL31_BASE should be the base address of the RAM region.
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*
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* Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
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* defined as default for our platform.
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*/
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#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */
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#define BL31_SIZE UL(0x00020000) /* 128k */
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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/*
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* Defines the maximum number of translation tables that are allocated by the
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* translation table library code. To minimize the amount of runtime memory
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* used, choose the smallest value needed to map the required virtual addresses
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* for each BL stage.
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*/
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#define MAX_XLAT_TABLES 4
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/*
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* Defines the maximum number of regions that are allocated by the translation
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* table library code. A region consists of physical base address, virtual base
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* address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
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* defined in the `mmap_region_t` structure. The platform defines the regions
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* that should be mapped. Then, the translation table library will create the
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* corresponding tables and descriptors at runtime. To minimize the amount of
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* runtime memory used, choose the smallest value needed to register the
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* required regions for each BL stage.
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*/
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#if USE_COHERENT_MEM
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#define MAX_MMAP_REGIONS 11
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#else
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#define MAX_MMAP_REGIONS 10
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#endif
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/*
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* Defines the total size of the address space in bytes. For example, for a 32
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* bit address space, this value should be `(1ull << 32)`.
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/* Platform default console definitions */
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#ifndef K3_USART_BASE
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#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART)
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#endif
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/* USART has a default size for address space */
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#define K3_USART_SIZE 0x1000
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#ifndef K3_USART_CLK_SPEED
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#define K3_USART_CLK_SPEED 48000000
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#endif
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/* Crash console defaults */
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#define CRASH_CONSOLE_BASE K3_USART_BASE
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#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
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#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
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/* Timer frequency */
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#ifndef SYS_COUNTER_FREQ_IN_TICKS
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#define SYS_COUNTER_FREQ_IN_TICKS 200000000
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#endif
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/* Interrupt numbers */
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define K3_GTC_BASE 0x00A90000
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/* We just need 20 byte offset, but simpler to just remap the 64K page in */
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#define K3_GTC_SIZE 0x10000
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#define K3_GTC_CNTCR_OFFSET 0x00
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#define K3_GTC_CNTCR_EN_MASK 0x01
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#define K3_GTC_CNTCR_HDBG_MASK 0x02
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#define K3_GTC_CNTFID0_OFFSET 0x20
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#define K3_GIC_BASE 0x01800000
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#define K3_GIC_SIZE 0x200000
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#define TI_SCI_HOST_ID 10
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#define TI_SCI_MAX_MESSAGE_SIZE 52
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#endif /* TI_PLATFORM_DEF_H */
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@ -55,7 +55,7 @@ PLAT_INCLUDES += \
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K3_CONSOLE_SOURCES += \
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drivers/ti/uart/aarch64/16550_console.S \
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${PLAT_PATH}/common/k3_console.c \
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plat/ti/common/k3_console.c \
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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@ -63,14 +63,11 @@ include drivers/arm/gic/v3/gicv3.mk
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K3_GIC_SOURCES += \
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${GICV3_SOURCES} \
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plat/common/plat_gicv3.c \
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${PLAT_PATH}/common/k3_gicv3.c \
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plat/ti/common/k3_gicv3.c \
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K3_PSCI_SOURCES += \
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plat/common/plat_psci_common.c \
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${PLAT_PATH}/common/k3_psci.c \
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K3_TI_SCI_TRANSPORT += \
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drivers/ti/ipc/sec_proxy.c \
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K3_TI_SCI_SOURCES += \
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drivers/ti/ti_sci/ti_sci.c \
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@ -82,11 +79,7 @@ PLAT_BL_COMMON_SOURCES += \
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${K3_CONSOLE_SOURCES} \
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BL31_SOURCES += \
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${PLAT_PATH}/common/k3_bl31_setup.c \
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${PLAT_PATH}/common/ti_bl31_setup.c \
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${PLAT_PATH}/common/k3_helpers.S \
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${PLAT_PATH}/common/k3_topology.c \
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plat/ti/common/ti_bl31_setup.c \
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plat/ti/common/k3_helpers.S \
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${K3_GIC_SOURCES} \
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${K3_PSCI_SOURCES} \
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${K3_TI_SCI_SOURCES} \
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${K3_TI_SCI_TRANSPORT} \
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@ -7,174 +7,7 @@
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <board_def.h>
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stack */
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#if IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#define PLATFORM_SYSTEM_COUNT 1
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#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
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K3_CLUSTER1_CORE_COUNT + \
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K3_CLUSTER2_CORE_COUNT + \
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K3_CLUSTER3_CORE_COUNT)
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#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \
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(K3_CLUSTER1_CORE_COUNT != 0) + \
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(K3_CLUSTER2_CORE_COUNT != 0) + \
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(K3_CLUSTER3_CORE_COUNT != 0))
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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/*******************************************************************************
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* Memory layout constants
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******************************************************************************/
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/*
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* This RAM will be used for the bootloader including code, bss, and stacks.
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* It may need to be increased if BL31 grows in size.
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*
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* The link addresses are determined by BL31_BASE + offset.
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* When ENABLE_PIE is set, the TF images can be loaded anywhere, so
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* BL31_BASE is really arbitrary.
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*
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* When ENABLE_PIE is unset, BL31_BASE should be chosen so that
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* it matches to the physical address where BL31 is loaded, that is,
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* BL31_BASE should be the base address of the RAM region.
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*
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* Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
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* defined as default for our platform.
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*/
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#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */
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#define BL31_SIZE UL(0x00020000) /* 128k */
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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/*
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* Defines the maximum number of translation tables that are allocated by the
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* translation table library code. To minimize the amount of runtime memory
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* used, choose the smallest value needed to map the required virtual addresses
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* for each BL stage.
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*/
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#define MAX_XLAT_TABLES 4
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/*
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* Defines the maximum number of regions that are allocated by the translation
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* table library code. A region consists of physical base address, virtual base
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* address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
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* defined in the `mmap_region_t` structure. The platform defines the regions
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* that should be mapped. Then, the translation table library will create the
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* corresponding tables and descriptors at runtime. To minimize the amount of
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* runtime memory used, choose the smallest value needed to register the
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* required regions for each BL stage.
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*/
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#if USE_COHERENT_MEM
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#define MAX_MMAP_REGIONS 11
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#else
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#define MAX_MMAP_REGIONS 10
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#endif
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/*
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* Defines the total size of the address space in bytes. For example, for a 32
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* bit address space, this value should be `(1ull << 32)`.
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/* Platform default console definitions */
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#ifndef K3_USART_BASE
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#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART)
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#endif
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/* USART has a default size for address space */
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#define K3_USART_SIZE 0x1000
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#ifndef K3_USART_CLK_SPEED
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#define K3_USART_CLK_SPEED 48000000
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#endif
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/* Crash console defaults */
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#define CRASH_CONSOLE_BASE K3_USART_BASE
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#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
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#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
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/* Timer frequency */
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#ifndef SYS_COUNTER_FREQ_IN_TICKS
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#define SYS_COUNTER_FREQ_IN_TICKS 200000000
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#endif
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/* Interrupt numbers */
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
|
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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#define K3_GTC_BASE 0x00A90000
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/* We just need 20 byte offset, but simpler to just remap the 64K page in */
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#define K3_GTC_SIZE 0x10000
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#define K3_GTC_CNTCR_OFFSET 0x00
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#define K3_GTC_CNTCR_EN_MASK 0x01
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#define K3_GTC_CNTCR_HDBG_MASK 0x02
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#define K3_GTC_CNTFID0_OFFSET 0x20
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#define K3_GIC_BASE 0x01800000
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#define K3_GIC_SIZE 0x200000
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#include <ti_platform_defs.h>
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#if !K3_SEC_PROXY_LITE
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#define SEC_PROXY_DATA_BASE 0x32C00000
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|
|
@ -195,7 +28,4 @@
|
|||
#define SEC_PROXY_TIMEOUT_US 1000000
|
||||
#define SEC_PROXY_MAX_MESSAGE_SIZE 56
|
||||
|
||||
#define TI_SCI_HOST_ID 10
|
||||
#define TI_SCI_MAX_MESSAGE_SIZE 52
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
PLAT_PATH := plat/ti/k3
|
||||
TARGET_BOARD ?= generic
|
||||
|
||||
include ${PLAT_PATH}/common/plat_common.mk
|
||||
include plat/ti/common/plat_common.mk
|
||||
include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk
|
||||
|
||||
BL32_BASE ?= 0x9e800000
|
||||
|
|
@ -19,7 +19,20 @@ $(eval $(call add_define,PRELOADED_BL33_BASE))
|
|||
K3_HW_CONFIG_BASE ?= 0x82000000
|
||||
$(eval $(call add_define,K3_HW_CONFIG_BASE))
|
||||
|
||||
PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include
|
||||
PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include \
|
||||
-Iplat/ti/common/include \
|
||||
|
||||
# modify BUILD_PLAT to point to board specific build directory
|
||||
BUILD_PLAT := $(abspath ${BUILD_BASE})/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE}
|
||||
|
||||
K3_PSCI_SOURCES += \
|
||||
${PLAT_PATH}/common/k3_psci.c \
|
||||
|
||||
K3_TI_SCI_TRANSPORT := \
|
||||
drivers/ti/ipc/sec_proxy.c \
|
||||
|
||||
BL31_SOURCES += \
|
||||
${PLAT_PATH}/common/k3_bl31_setup.c \
|
||||
${PLAT_PATH}/common/k3_topology.c \
|
||||
${K3_TI_SCI_TRANSPORT} \
|
||||
${K3_PSCI_SOURCES} \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue