From bfac44b51b52f95a889bdc656dd8828665f4c1f5 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Mon, 24 Mar 2025 11:12:58 +0530 Subject: [PATCH] refactor(ti): move out k3/common to ti/common This will allow us to support more platforms that share commonalities like the k3_gicv3, console, helpers, etc. With this new common folder location, we can move the previously created ti_bl31_setup file into the new location so it can be shared across multiple TI SoCs when need comes. With this, also update all copyright dates. Change-Id: Ie4365e32cd3b4b5870fe2cd03843400506e46265 Signed-off-by: Dhruva Gole --- plat/ti/{k3 => common}/include/k3_console.h | 0 plat/ti/{k3 => common}/include/k3_gicv3.h | 0 plat/ti/{k3 => common}/include/plat_macros.S | 0 plat/ti/{k3 => common}/include/plat_private.h | 0 plat/ti/common/include/ti_platform_defs.h | 182 ++++++++++++++++++ plat/ti/{k3 => }/common/k3_console.c | 0 plat/ti/{k3 => }/common/k3_gicv3.c | 0 plat/ti/{k3 => }/common/k3_helpers.S | 0 plat/ti/{k3 => }/common/plat_common.mk | 15 +- plat/ti/{k3 => }/common/ti_bl31_setup.c | 0 plat/ti/k3/include/platform_def.h | 172 +---------------- plat/ti/k3/platform.mk | 17 +- 12 files changed, 202 insertions(+), 184 deletions(-) rename plat/ti/{k3 => common}/include/k3_console.h (100%) rename plat/ti/{k3 => common}/include/k3_gicv3.h (100%) rename plat/ti/{k3 => common}/include/plat_macros.S (100%) rename plat/ti/{k3 => common}/include/plat_private.h (100%) create mode 100644 plat/ti/common/include/ti_platform_defs.h rename plat/ti/{k3 => }/common/k3_console.c (100%) rename plat/ti/{k3 => }/common/k3_gicv3.c (100%) rename plat/ti/{k3 => }/common/k3_helpers.S (100%) rename plat/ti/{k3 => }/common/plat_common.mk (82%) rename plat/ti/{k3 => }/common/ti_bl31_setup.c (100%) diff --git a/plat/ti/k3/include/k3_console.h b/plat/ti/common/include/k3_console.h similarity index 100% rename from plat/ti/k3/include/k3_console.h rename to plat/ti/common/include/k3_console.h diff --git a/plat/ti/k3/include/k3_gicv3.h b/plat/ti/common/include/k3_gicv3.h similarity index 100% rename from plat/ti/k3/include/k3_gicv3.h rename to plat/ti/common/include/k3_gicv3.h diff --git a/plat/ti/k3/include/plat_macros.S b/plat/ti/common/include/plat_macros.S similarity index 100% rename from plat/ti/k3/include/plat_macros.S rename to plat/ti/common/include/plat_macros.S diff --git a/plat/ti/k3/include/plat_private.h b/plat/ti/common/include/plat_private.h similarity index 100% rename from plat/ti/k3/include/plat_private.h rename to plat/ti/common/include/plat_private.h diff --git a/plat/ti/common/include/ti_platform_defs.h b/plat/ti/common/include/ti_platform_defs.h new file mode 100644 index 000000000..44c2f94c3 --- /dev/null +++ b/plat/ti/common/include/ti_platform_defs.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TI_PLATFORM_DEF_H +#define TI_PLATFORM_DEF_H + +#include +#include + +#include + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stack */ +#if IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#else +#define PLATFORM_STACK_SIZE 0x1000 +#endif + +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ + K3_CLUSTER1_CORE_COUNT + \ + K3_CLUSTER2_CORE_COUNT + \ + K3_CLUSTER3_CORE_COUNT) + +#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \ + (K3_CLUSTER1_CORE_COUNT != 0) + \ + (K3_CLUSTER2_CORE_COUNT != 0) + \ + (K3_CLUSTER3_CORE_COUNT != 0)) + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) + +/******************************************************************************* + * Memory layout constants + ******************************************************************************/ + +/* + * This RAM will be used for the bootloader including code, bss, and stacks. + * It may need to be increased if BL31 grows in size. + * + * The link addresses are determined by BL31_BASE + offset. + * When ENABLE_PIE is set, the TF images can be loaded anywhere, so + * BL31_BASE is really arbitrary. + * + * When ENABLE_PIE is unset, BL31_BASE should be chosen so that + * it matches to the physical address where BL31 is loaded, that is, + * BL31_BASE should be the base address of the RAM region. + * + * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is + * defined as default for our platform. + */ +#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */ +#define BL31_SIZE UL(0x00020000) /* 128k */ +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* + * Defines the maximum number of translation tables that are allocated by the + * translation table library code. To minimize the amount of runtime memory + * used, choose the smallest value needed to map the required virtual addresses + * for each BL stage. + */ +#define MAX_XLAT_TABLES 4 + +/* + * Defines the maximum number of regions that are allocated by the translation + * table library code. A region consists of physical base address, virtual base + * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as + * defined in the `mmap_region_t` structure. The platform defines the regions + * that should be mapped. Then, the translation table library will create the + * corresponding tables and descriptors at runtime. To minimize the amount of + * runtime memory used, choose the smallest value needed to register the + * required regions for each BL stage. + */ +#if USE_COHERENT_MEM +#define MAX_MMAP_REGIONS 11 +#else +#define MAX_MMAP_REGIONS 10 +#endif + +/* + * Defines the total size of the address space in bytes. For example, for a 32 + * bit address space, this value should be `(1ull << 32)`. + */ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* Platform default console definitions */ +#ifndef K3_USART_BASE +#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART) +#endif + +/* USART has a default size for address space */ +#define K3_USART_SIZE 0x1000 + +#ifndef K3_USART_CLK_SPEED +#define K3_USART_CLK_SPEED 48000000 +#endif + +/* Crash console defaults */ +#define CRASH_CONSOLE_BASE K3_USART_BASE +#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED +#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD + +/* Timer frequency */ +#ifndef SYS_COUNTER_FREQ_IN_TICKS +#define SYS_COUNTER_FREQ_IN_TICKS 200000000 +#endif + +/* Interrupt numbers */ +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_EDGE) + + +#define K3_GTC_BASE 0x00A90000 +/* We just need 20 byte offset, but simpler to just remap the 64K page in */ +#define K3_GTC_SIZE 0x10000 +#define K3_GTC_CNTCR_OFFSET 0x00 +#define K3_GTC_CNTCR_EN_MASK 0x01 +#define K3_GTC_CNTCR_HDBG_MASK 0x02 +#define K3_GTC_CNTFID0_OFFSET 0x20 + +#define K3_GIC_BASE 0x01800000 +#define K3_GIC_SIZE 0x200000 + +#define TI_SCI_HOST_ID 10 +#define TI_SCI_MAX_MESSAGE_SIZE 52 + +#endif /* TI_PLATFORM_DEF_H */ diff --git a/plat/ti/k3/common/k3_console.c b/plat/ti/common/k3_console.c similarity index 100% rename from plat/ti/k3/common/k3_console.c rename to plat/ti/common/k3_console.c diff --git a/plat/ti/k3/common/k3_gicv3.c b/plat/ti/common/k3_gicv3.c similarity index 100% rename from plat/ti/k3/common/k3_gicv3.c rename to plat/ti/common/k3_gicv3.c diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/common/k3_helpers.S similarity index 100% rename from plat/ti/k3/common/k3_helpers.S rename to plat/ti/common/k3_helpers.S diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/common/plat_common.mk similarity index 82% rename from plat/ti/k3/common/plat_common.mk rename to plat/ti/common/plat_common.mk index 3a756c128..1f1b61858 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/common/plat_common.mk @@ -55,7 +55,7 @@ PLAT_INCLUDES += \ K3_CONSOLE_SOURCES += \ drivers/ti/uart/aarch64/16550_console.S \ - ${PLAT_PATH}/common/k3_console.c \ + plat/ti/common/k3_console.c \ # Include GICv3 driver files include drivers/arm/gic/v3/gicv3.mk @@ -63,14 +63,11 @@ include drivers/arm/gic/v3/gicv3.mk K3_GIC_SOURCES += \ ${GICV3_SOURCES} \ plat/common/plat_gicv3.c \ - ${PLAT_PATH}/common/k3_gicv3.c \ + plat/ti/common/k3_gicv3.c \ K3_PSCI_SOURCES += \ plat/common/plat_psci_common.c \ - ${PLAT_PATH}/common/k3_psci.c \ -K3_TI_SCI_TRANSPORT += \ - drivers/ti/ipc/sec_proxy.c \ K3_TI_SCI_SOURCES += \ drivers/ti/ti_sci/ti_sci.c \ @@ -82,11 +79,7 @@ PLAT_BL_COMMON_SOURCES += \ ${K3_CONSOLE_SOURCES} \ BL31_SOURCES += \ - ${PLAT_PATH}/common/k3_bl31_setup.c \ - ${PLAT_PATH}/common/ti_bl31_setup.c \ - ${PLAT_PATH}/common/k3_helpers.S \ - ${PLAT_PATH}/common/k3_topology.c \ + plat/ti/common/ti_bl31_setup.c \ + plat/ti/common/k3_helpers.S \ ${K3_GIC_SOURCES} \ - ${K3_PSCI_SOURCES} \ ${K3_TI_SCI_SOURCES} \ - ${K3_TI_SCI_TRANSPORT} \ diff --git a/plat/ti/k3/common/ti_bl31_setup.c b/plat/ti/common/ti_bl31_setup.c similarity index 100% rename from plat/ti/k3/common/ti_bl31_setup.c rename to plat/ti/common/ti_bl31_setup.c diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h index a2cc62d34..db5e31d95 100644 --- a/plat/ti/k3/include/platform_def.h +++ b/plat/ti/k3/include/platform_def.h @@ -7,174 +7,7 @@ #ifndef PLATFORM_DEF_H #define PLATFORM_DEF_H -#include -#include - -#include - -/******************************************************************************* - * Generic platform constants - ******************************************************************************/ - -/* Size of cacheable stack */ -#if IMAGE_BL31 -#define PLATFORM_STACK_SIZE 0x800 -#else -#define PLATFORM_STACK_SIZE 0x1000 -#endif - -#define PLATFORM_SYSTEM_COUNT 1 -#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \ - K3_CLUSTER1_CORE_COUNT + \ - K3_CLUSTER2_CORE_COUNT + \ - K3_CLUSTER3_CORE_COUNT) - -#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \ - (K3_CLUSTER1_CORE_COUNT != 0) + \ - (K3_CLUSTER2_CORE_COUNT != 0) + \ - (K3_CLUSTER3_CORE_COUNT != 0)) - -#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ - PLATFORM_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) -#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 -#define PLAT_MAX_OFF_STATE U(2) -#define PLAT_MAX_RET_STATE U(1) - -/******************************************************************************* - * Memory layout constants - ******************************************************************************/ - -/* - * This RAM will be used for the bootloader including code, bss, and stacks. - * It may need to be increased if BL31 grows in size. - * - * The link addresses are determined by BL31_BASE + offset. - * When ENABLE_PIE is set, the TF images can be loaded anywhere, so - * BL31_BASE is really arbitrary. - * - * When ENABLE_PIE is unset, BL31_BASE should be chosen so that - * it matches to the physical address where BL31 is loaded, that is, - * BL31_BASE should be the base address of the RAM region. - * - * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is - * defined as default for our platform. - */ -#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */ -#define BL31_SIZE UL(0x00020000) /* 128k */ -#define BL31_LIMIT (BL31_BASE + BL31_SIZE) - -/* - * Defines the maximum number of translation tables that are allocated by the - * translation table library code. To minimize the amount of runtime memory - * used, choose the smallest value needed to map the required virtual addresses - * for each BL stage. - */ -#define MAX_XLAT_TABLES 4 - -/* - * Defines the maximum number of regions that are allocated by the translation - * table library code. A region consists of physical base address, virtual base - * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as - * defined in the `mmap_region_t` structure. The platform defines the regions - * that should be mapped. Then, the translation table library will create the - * corresponding tables and descriptors at runtime. To minimize the amount of - * runtime memory used, choose the smallest value needed to register the - * required regions for each BL stage. - */ -#if USE_COHERENT_MEM -#define MAX_MMAP_REGIONS 11 -#else -#define MAX_MMAP_REGIONS 10 -#endif - -/* - * Defines the total size of the address space in bytes. For example, for a 32 - * bit address space, this value should be `(1ull << 32)`. - */ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) - -/* - * Some data must be aligned on the biggest cache line size in the platform. - * This is known only to the platform as it might have a combination of - * integrated and external caches. - */ -#define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -/* Platform default console definitions */ -#ifndef K3_USART_BASE -#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART) -#endif - -/* USART has a default size for address space */ -#define K3_USART_SIZE 0x1000 - -#ifndef K3_USART_CLK_SPEED -#define K3_USART_CLK_SPEED 48000000 -#endif - -/* Crash console defaults */ -#define CRASH_CONSOLE_BASE K3_USART_BASE -#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED -#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD - -/* Timer frequency */ -#ifndef SYS_COUNTER_FREQ_IN_TICKS -#define SYS_COUNTER_FREQ_IN_TICKS 200000000 -#endif - -/* Interrupt numbers */ -#define ARM_IRQ_SEC_PHY_TIMER 29 - -#define ARM_IRQ_SEC_SGI_0 8 -#define ARM_IRQ_SEC_SGI_1 9 -#define ARM_IRQ_SEC_SGI_2 10 -#define ARM_IRQ_SEC_SGI_3 11 -#define ARM_IRQ_SEC_SGI_4 12 -#define ARM_IRQ_SEC_SGI_5 13 -#define ARM_IRQ_SEC_SGI_6 14 -#define ARM_IRQ_SEC_SGI_7 15 - -/* - * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 - * terminology. On a GICv2 system or mode, the lists will be merged and treated - * as Group 0 interrupts. - */ -#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE) - -#define PLAT_ARM_G0_IRQ_PROPS(grp) \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE) - - -#define K3_GTC_BASE 0x00A90000 -/* We just need 20 byte offset, but simpler to just remap the 64K page in */ -#define K3_GTC_SIZE 0x10000 -#define K3_GTC_CNTCR_OFFSET 0x00 -#define K3_GTC_CNTCR_EN_MASK 0x01 -#define K3_GTC_CNTCR_HDBG_MASK 0x02 -#define K3_GTC_CNTFID0_OFFSET 0x20 - -#define K3_GIC_BASE 0x01800000 -#define K3_GIC_SIZE 0x200000 +#include #if !K3_SEC_PROXY_LITE #define SEC_PROXY_DATA_BASE 0x32C00000 @@ -195,7 +28,4 @@ #define SEC_PROXY_TIMEOUT_US 1000000 #define SEC_PROXY_MAX_MESSAGE_SIZE 56 -#define TI_SCI_HOST_ID 10 -#define TI_SCI_MAX_MESSAGE_SIZE 52 - #endif /* PLATFORM_DEF_H */ diff --git a/plat/ti/k3/platform.mk b/plat/ti/k3/platform.mk index bce9ef176..347a08894 100644 --- a/plat/ti/k3/platform.mk +++ b/plat/ti/k3/platform.mk @@ -7,7 +7,7 @@ PLAT_PATH := plat/ti/k3 TARGET_BOARD ?= generic -include ${PLAT_PATH}/common/plat_common.mk +include plat/ti/common/plat_common.mk include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk BL32_BASE ?= 0x9e800000 @@ -19,7 +19,20 @@ $(eval $(call add_define,PRELOADED_BL33_BASE)) K3_HW_CONFIG_BASE ?= 0x82000000 $(eval $(call add_define,K3_HW_CONFIG_BASE)) -PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include +PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include \ + -Iplat/ti/common/include \ # modify BUILD_PLAT to point to board specific build directory BUILD_PLAT := $(abspath ${BUILD_BASE})/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE} + +K3_PSCI_SOURCES += \ + ${PLAT_PATH}/common/k3_psci.c \ + +K3_TI_SCI_TRANSPORT := \ + drivers/ti/ipc/sec_proxy.c \ + +BL31_SOURCES += \ + ${PLAT_PATH}/common/k3_bl31_setup.c \ + ${PLAT_PATH}/common/k3_topology.c \ + ${K3_TI_SCI_TRANSPORT} \ + ${K3_PSCI_SOURCES} \