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https://github.com/ARM-software/arm-trusted-firmware.git
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nxp: add flexspi driver support
Flexspi driver now introduces read/write/erase APIs for complete flash size, FAST-READ are by default used and IP bus is used for erase, read and write using flexspi APIs. Framework layer is currently embedded in driver itself using flash_info defines. Test cases are also added to confirm flash functionality currently under DEBUG flag. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
This commit is contained in:
Kuldeep Singh
Pankaj Gupta
parent
b53334dac4
commit
b525a8f0d2
9 changed files with 1615 additions and 0 deletions
25
drivers/nxp/flexspi/nor/flexspi_nor.c
Normal file
25
drivers/nxp/flexspi/nor/flexspi_nor.c
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@ -0,0 +1,25 @@
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <fspi_api.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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int flexspi_nor_io_setup(uintptr_t nxp_flexspi_flash_addr,
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size_t nxp_flexspi_flash_size, uint32_t fspi_base_reg_addr)
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{
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int ret = 0;
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ret = fspi_init(fspi_base_reg_addr, nxp_flexspi_flash_addr);
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/* Adding NOR Memory Map in XLAT Table */
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mmap_add_region(nxp_flexspi_flash_addr, nxp_flexspi_flash_addr,
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nxp_flexspi_flash_size, MT_MEMORY | MT_RW);
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return ret;
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}
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15
drivers/nxp/flexspi/nor/flexspi_nor.h
Normal file
15
drivers/nxp/flexspi/nor/flexspi_nor.h
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@ -0,0 +1,15 @@
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef FLEXSPI_NOR_H
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#define FLEXSPI_NOR_H
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int flexspi_nor_io_setup(uintptr_t nxp_flexspi_flash_addr,
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size_t nxp_flexspi_flash_size,
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uint32_t fspi_base_reg_addr);
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#endif /* FLEXSPI_NOR_H */
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35
drivers/nxp/flexspi/nor/flexspi_nor.mk
Normal file
35
drivers/nxp/flexspi/nor/flexspi_nor.mk
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@ -0,0 +1,35 @@
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#
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# Copyright 2020 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifeq (${XSPI_NOR},)
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XSPI_NOR := 1
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FLEXSPI_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/flexspi/nor
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PLAT_XSPI_INCLUDES += -I$(FLEXSPI_DRIVERS_PATH)
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XSPI_BOOT_SOURCES += $(FLEXSPI_DRIVERS_PATH)/flexspi_nor.c \
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${FLEXSPI_DRIVERS_PATH}/fspi.c
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ifeq ($(DEBUG),1)
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XSPI_BOOT_SOURCES += ${FLEXSPI_DRIVERS_PATH}/test_fspi.c
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endif
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PLAT_XSPI_INCLUDES += -Iinclude/drivers/nxp/flexspi
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PLAT_INCLUDES += ${PLAT_XSPI_INCLUDES}
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ifeq (${BL_COMM_XSPI_NEEDED},yes)
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BL_COMMON_SOURCES += ${XSPI_BOOT_SOURCES}
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else
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ifeq (${BL2_XSPI_NEEDED},yes)
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BL2_SOURCES += ${XSPI_BOOT_SOURCES}
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endif
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ifeq (${BL31_XSPI_NEEDED},yes)
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BL31_SOURCES += ${XSPI_BOOT_SOURCES}
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endif
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endif
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endif
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853
drivers/nxp/flexspi/nor/fspi.c
Normal file
853
drivers/nxp/flexspi/nor/fspi.c
Normal file
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@ -0,0 +1,853 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* NXP FlexSpi Controller Driver.
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* Copyright 2021 NXP
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*
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*/
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#include <endian.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <common/debug.h>
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#include <flash_info.h>
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#include "fspi.h"
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#include <fspi_api.h>
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#include <xspi_error_codes.h>
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#ifdef DEBUG_FLEXSPI
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#define PR printf("In [%s][%d]\n", __func__, __LINE__)
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#define PRA(a, b) printf("In [%s][%d] %s="a"\n", __func__, __LINE__, #b, b)
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#else
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#define PR
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#define PRA(a, b)
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#endif
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/*
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* This errata is valid for all NXP SoC.
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*/
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#define ERRATA_FLASH_A050272 1
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static uintptr_t fspi_base_reg_addr;
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static uintptr_t fspi_flash_base_addr;
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static void fspi_RDSR(uint32_t *, const void *, uint32_t);
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static void fspi_writel(uint32_t x_addr, uint32_t x_val)
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{
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fspi_out32((uint32_t *)(fspi_base_reg_addr + x_addr),
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(uint32_t) x_val);
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}
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static uint32_t fspi_readl(uint32_t x_addr)
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{
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return fspi_in32((uint32_t *)(fspi_base_reg_addr + x_addr));
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}
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static void fspi_MDIS(uint8_t x_disable)
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{
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uint32_t ui_reg;
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ui_reg = fspi_readl(FSPI_MCR0);
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if (x_disable != 0U) {
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ui_reg |= FSPI_MCR0_MDIS;
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} else {
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ui_reg &= (uint32_t) (~FSPI_MCR0_MDIS);
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}
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fspi_writel(FSPI_MCR0, ui_reg);
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}
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static void fspi_lock_LUT(void)
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{
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fspi_writel(FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
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VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));
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fspi_writel(FSPI_LCKCR, FSPI_LCKER_LOCK);
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VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));
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}
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static void fspi_unlock_LUT(void)
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{
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fspi_writel(FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
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VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));
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fspi_writel(FSPI_LCKCR, FSPI_LCKER_UNLOCK);
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VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));
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}
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static void fspi_op_setup(uint32_t fspi_op_seq_id, bool ignore_flash_sz)
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{
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uint32_t x_addr, x_instr0 = 0, x_instr1 = 0, x_instr2 = 0;
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uint32_t cmd_id1, cmd_id2;
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VERBOSE("In func %s\n", __func__);
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switch (fspi_op_seq_id) {
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case FSPI_READ_SEQ_ID:
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cmd_id1 = FSPI_NOR_CMD_READ;
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cmd_id2 = FSPI_NOR_CMD_READ_4B;
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x_instr2 = FSPI_INSTR_OPRND0(0) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1)
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| FSPI_INSTR_OPCODE0(FSPI_LUT_READ);
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break;
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case FSPI_FASTREAD_SEQ_ID:
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cmd_id1 = FSPI_NOR_CMD_FASTREAD;
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cmd_id2 = FSPI_NOR_CMD_FASTREAD_4B;
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x_instr2 = FSPI_INSTR_OPRND0(8) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1)
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| FSPI_INSTR_OPCODE0(FSPI_DUMMY_SDR)
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| FSPI_INSTR_OPRND1(0)
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| FSPI_INSTR_PAD1(FSPI_LUT_PAD1)
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| FSPI_INSTR_OPCODE1(FSPI_LUT_READ);
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break;
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case FSPI_WRITE_SEQ_ID:
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cmd_id1 = FSPI_NOR_CMD_PP;
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cmd_id2 = FSPI_NOR_CMD_PP_4B;
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x_instr2 = FSPI_INSTR_OPRND0(0) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1)
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| FSPI_INSTR_OPCODE0(FSPI_LUT_WRITE);
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break;
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case FSPI_WREN_SEQ_ID:
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cmd_id1 = FSPI_NOR_CMD_WREN;
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cmd_id2 = FSPI_NOR_CMD_WREN;
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break;
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case FSPI_SE_SEQ_ID:
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cmd_id1 = FSPI_NOR_CMD_SE_64K;
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cmd_id2 = FSPI_NOR_CMD_SE_64K_4B;
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break;
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case FSPI_4K_SEQ_ID:
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cmd_id1 = FSPI_NOR_CMD_SE_4K;
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cmd_id2 = FSPI_NOR_CMD_SE_4K_4B;
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break;
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case FSPI_BE_SEQ_ID:
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cmd_id1 = FSPI_NOR_CMD_BE;
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cmd_id2 = FSPI_NOR_CMD_BE;
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break;
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case FSPI_RDSR_SEQ_ID:
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cmd_id1 = FSPI_NOR_CMD_RDSR;
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cmd_id2 = FSPI_NOR_CMD_RDSR;
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break;
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}
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x_addr = FSPI_LUTREG_OFFSET + (uint32_t)(0x10 * fspi_op_seq_id);
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if ((F_FLASH_SIZE_BYTES <= SZ_16M_BYTES) || (ignore_flash_sz)) {
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x_instr0 = FSPI_INSTR_OPRND0(cmd_id1);
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x_instr1 = FSPI_INSTR_OPRND1(FSPI_LUT_ADDR24BIT);
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VERBOSE("CMD_ID = %x offset = 0x%x\n", cmd_id1, x_addr);
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} else {
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x_instr0 = FSPI_INSTR_OPRND0(cmd_id2);
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x_instr1 = FSPI_INSTR_OPRND1(FSPI_LUT_ADDR32BIT);
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VERBOSE("CMD_ID = %x offset = 0x%x\n", cmd_id2, x_addr);
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}
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x_instr0 |= FSPI_INSTR_PAD0(FSPI_LUT_PAD1)
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| FSPI_INSTR_OPCODE0(FSPI_LUT_CMD);
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x_instr1 |= FSPI_INSTR_PAD1(FSPI_LUT_PAD1)
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| FSPI_INSTR_OPCODE1(FSPI_LUT_ADDR);
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if (fspi_op_seq_id == FSPI_RDSR_SEQ_ID) {
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x_instr0 |= FSPI_INSTR_OPRND1(1) | FSPI_INSTR_PAD1(FSPI_LUT_PAD1)
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| FSPI_INSTR_OPCODE1(FSPI_LUT_READ);
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} else if ((fspi_op_seq_id != FSPI_BE_SEQ_ID)
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&& (fspi_op_seq_id != FSPI_WREN_SEQ_ID)) {
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x_instr0 |= x_instr1;
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}
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fspi_writel((x_addr), x_instr0);
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fspi_writel((x_addr + U(0x4)), x_instr2);
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fspi_writel((x_addr + U(0x8)), (uint32_t) 0x0); /* STOP command */
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fspi_writel((x_addr + U(0xc)), (uint32_t) 0x0); /* STOP command */
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}
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static void fspi_setup_LUT(void)
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{
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VERBOSE("In func %s\n", __func__);
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fspi_unlock_LUT();
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/* LUT Setup for READ Command 3-Byte low Frequency */
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fspi_op_setup(FSPI_READ_SEQ_ID, false);
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/* LUT Setup for FAST READ Command 3-Byte/4-Byte high Frequency */
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fspi_op_setup(FSPI_FASTREAD_SEQ_ID, false);
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/* LUT Setup for Page Program */
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fspi_op_setup(FSPI_WRITE_SEQ_ID, false);
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/* LUT Setup for WREN */
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fspi_op_setup(FSPI_WREN_SEQ_ID, true);
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/* LUT Setup for Sector_Erase */
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fspi_op_setup(FSPI_SE_SEQ_ID, false);
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/* LUT Setup for Sub Sector 4K Erase */
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fspi_op_setup(FSPI_4K_SEQ_ID, false);
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/* LUT Setup for Bulk_Erase */
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fspi_op_setup(FSPI_BE_SEQ_ID, true);
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/* Read Status */
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fspi_op_setup(FSPI_RDSR_SEQ_ID, true);
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fspi_lock_LUT();
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}
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static inline void fspi_ahb_invalidate(void)
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{
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uint32_t reg;
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VERBOSE("In func %s %d\n", __func__, __LINE__);
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reg = fspi_readl(FSPI_MCR0);
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reg |= FSPI_MCR0_SWRST;
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fspi_writel(FSPI_MCR0, reg);
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while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST) != 0)
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; /* FSPI_MCR0_SWRESET_MASK */
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VERBOSE("In func %s %d\n", __func__, __LINE__);
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}
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#if defined(CONFIG_FSPI_AHB)
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static void fspi_init_ahb(void)
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{
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uint32_t i, x_flash_cr2, seq_id;
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x_flash_cr2 = 0;
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/* Reset AHB RX buffer CR configuration */
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for (i = 0; i < 8; i++) {
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fspi_writel((FSPI_AHBRX_BUF0CR0 + 4 * i), 0U);
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}
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/* Set ADATSZ with the maximum AHB buffer size */
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fspi_writel(FSPI_AHBRX_BUF7CR0,
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((uint32_t) ((FSPI_RX_MAX_AHBBUF_SIZE / 8U) |
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FSPI_AHBRXBUF0CR7_PREF)));
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/* Known limitation handling: prefetch and
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* no start address alignment.*/
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fspi_writel(FSPI_AHBCR, FSPI_AHBCR_PREF_EN);
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INFO("xAhbcr=0x%x\n", fspi_readl(FSPI_AHBCR));
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// Setup AHB READ sequenceID for all flashes.
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x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2);
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INFO("x_flash_cr2=0x%x\n", x_flash_cr2);
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seq_id = CONFIG_FSPI_FASTREAD ?
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FSPI_FASTREAD_SEQ_ID : FSPI_READ_SEQ_ID;
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x_flash_cr2 |= ((seq_id << FSPI_FLSHXCR2_ARDSEQI_SHIFT) & 0x1f);
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INFO("x_flash_cr2=0x%x\n", x_flash_cr2);
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fspi_writel(FSPI_FLSHA1CR2, x_flash_cr2);
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x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2);
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INFO("x_flash_cr2=0x%x\n", x_flash_cr2);
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}
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#endif
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int xspi_read(uint32_t pc_rx_addr, uint32_t *pc_rx_buf, uint32_t x_size_bytes)
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{
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if (x_size_bytes == 0) {
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ERROR("Zero length reads are not allowed\n");
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return XSPI_READ_FAIL;
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}
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#if defined(CONFIG_FSPI_AHB)
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||||||
|
return xspi_ahb_read(pc_rx_addr, pc_rx_buf, x_size_bytes);
|
||||||
|
#else
|
||||||
|
return xspi_ip_read(pc_rx_addr, pc_rx_buf, x_size_bytes);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#if defined(CONFIG_FSPI_AHB)
|
||||||
|
int xspi_ahb_read(uint32_t pc_rx_addr, uint32_t *pc_rx_buf, uint32_t x_size_bytes)
|
||||||
|
{
|
||||||
|
VERBOSE("In func %s 0x%x\n", __func__, (pc_rx_addr));
|
||||||
|
|
||||||
|
if (F_FLASH_SIZE_BYTES <= SZ_16M_BYTES) {
|
||||||
|
pc_rx_addr = ((uint32_t)(pcRxAddr & MASK_24BIT_ADDRESS));
|
||||||
|
} else {
|
||||||
|
pc_rx_addr = ((uint32_t)(pcRxAddr & MASK_32BIT_ADDRESS));
|
||||||
|
}
|
||||||
|
|
||||||
|
pc_rx_addr = ((uint32_t)(pcRxAddr + fspi_flash_base_addr));
|
||||||
|
|
||||||
|
if (((pc_rx_addr % 4) != 0) || (((uintptr_t)pc_rx_buf % 4) != 0)) {
|
||||||
|
WARN("%s: unaligned Start Address src=%ld dst=0x%p\n",
|
||||||
|
__func__, (pc_rx_addr - fspi_flash_base_addr), pc_rx_buf);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Directly copy from AHB Buffer */
|
||||||
|
memcpy(pc_rx_buf, (void *)(uintptr_t)pc_rx_addr, x_size_bytes);
|
||||||
|
|
||||||
|
fspi_ahb_invalidate();
|
||||||
|
return XSPI_SUCCESS;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int xspi_ip_read(uint32_t pc_rx_addr, uint32_t *pv_rx_buf, uint32_t ui_len)
|
||||||
|
{
|
||||||
|
|
||||||
|
uint32_t i = 0U, j = 0U, x_rem = 0U;
|
||||||
|
uint32_t x_iteration = 0U, x_size_rx = 0U, x_size_wm, temp_size;
|
||||||
|
uint32_t data = 0U;
|
||||||
|
uint32_t x_len_bytes;
|
||||||
|
uint32_t x_addr, sts0, intr, seq_id;
|
||||||
|
|
||||||
|
x_addr = (uint32_t) pc_rx_addr;
|
||||||
|
x_len_bytes = ui_len;
|
||||||
|
|
||||||
|
/* Watermark level : 8 bytes. (BY DEFAULT) */
|
||||||
|
x_size_wm = 8U;
|
||||||
|
|
||||||
|
/* Clear RX Watermark interrupt in INT register, if any existing. */
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA);
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_INTR));
|
||||||
|
/* Invalid the RXFIFO, to run next IP Command */
|
||||||
|
/* Clears data entries in IP Rx FIFOs, Also reset R/W pointers */
|
||||||
|
fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR);
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTEN_IPCMDDONE);
|
||||||
|
|
||||||
|
while (x_len_bytes) {
|
||||||
|
|
||||||
|
/* FlexSPI can store no more than FSPI_RX_IPBUF_SIZE */
|
||||||
|
x_size_rx = (x_len_bytes > FSPI_RX_IPBUF_SIZE) ?
|
||||||
|
FSPI_RX_IPBUF_SIZE : x_len_bytes;
|
||||||
|
|
||||||
|
/* IP Control Register0 - SF Address to be read */
|
||||||
|
fspi_writel(FSPI_IPCR0, x_addr);
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_IPCR0));
|
||||||
|
/* IP Control Register1 - SEQID_READ operation, Size */
|
||||||
|
|
||||||
|
seq_id = CONFIG_FSPI_FASTREAD ?
|
||||||
|
FSPI_FASTREAD_SEQ_ID : FSPI_READ_SEQ_ID;
|
||||||
|
|
||||||
|
fspi_writel(FSPI_IPCR1,
|
||||||
|
(uint32_t)(seq_id << FSPI_IPCR1_ISEQID_SHIFT) |
|
||||||
|
(uint16_t) x_size_rx);
|
||||||
|
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_IPCR1));
|
||||||
|
|
||||||
|
do {
|
||||||
|
sts0 = fspi_readl(FSPI_STS0);
|
||||||
|
} while (((sts0 & FSPI_STS0_ARB_IDLE) == 0) &&
|
||||||
|
((sts0 & FSPI_STS0_SEQ_IDLE) == 0));
|
||||||
|
|
||||||
|
/* Trigger IP Read Command */
|
||||||
|
fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_IPCMD));
|
||||||
|
|
||||||
|
intr = fspi_readl(FSPI_INTR);
|
||||||
|
if (((intr & FSPI_INTR_IPCMDGE) != 0) ||
|
||||||
|
((intr & FSPI_INTR_IPCMDERR) != 0)) {
|
||||||
|
ERROR("Error in IP READ INTR=0x%x\n", intr);
|
||||||
|
return -XSPI_IP_READ_FAIL;
|
||||||
|
}
|
||||||
|
/* Will read in n iterations of each 8 FIFO's(WM level) */
|
||||||
|
x_iteration = x_size_rx / x_size_wm;
|
||||||
|
for (i = 0U; i < x_iteration; i++) {
|
||||||
|
if ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK) == 0) {
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_INTR));
|
||||||
|
}
|
||||||
|
/* Wait for IP Rx Watermark Fill event */
|
||||||
|
while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK)) {
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_INTR));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Read RX FIFO's(upto WM level) & copy to rxbuffer */
|
||||||
|
for (j = 0U; j < x_size_wm; j += 4U) {
|
||||||
|
/* Read FIFO Data Register */
|
||||||
|
data = fspi_readl(FSPI_RFDR + j);
|
||||||
|
#if FSPI_IPDATA_SWAP /* Just In case you want swap */
|
||||||
|
data = bswap32(data);
|
||||||
|
#endif
|
||||||
|
memcpy(pv_rx_buf++, &data, 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear IP_RX_WATERMARK Event in INTR register */
|
||||||
|
/* Reset FIFO Read pointer for next iteration.*/
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA);
|
||||||
|
}
|
||||||
|
|
||||||
|
x_rem = x_size_rx % x_size_wm;
|
||||||
|
|
||||||
|
if (x_rem != 0U) {
|
||||||
|
/* Wait for data filled */
|
||||||
|
while (!(fspi_readl(FSPI_IPRXFSTS) & FSPI_IPRXFSTS_FILL_MASK)) {
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_IPRXFSTS));
|
||||||
|
}
|
||||||
|
|
||||||
|
temp_size = 0;
|
||||||
|
j = 0U;
|
||||||
|
while (x_rem > 0U) {
|
||||||
|
data = 0U;
|
||||||
|
data = fspi_readl(FSPI_RFDR + j);
|
||||||
|
#if FSPI_IPDATA_SWAP /* Just In case you want swap */
|
||||||
|
data = bswap32(data);
|
||||||
|
#endif
|
||||||
|
temp_size = (x_rem < 4) ? x_rem : 4;
|
||||||
|
memcpy(pv_rx_buf++, &data, temp_size);
|
||||||
|
x_rem -= temp_size;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK)) {
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_INTR));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Invalid the RX FIFO, to run next IP Command */
|
||||||
|
fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR);
|
||||||
|
/* Clear IP Command Done flag in interrupt register*/
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
|
||||||
|
|
||||||
|
/* Update remaining len, Increment x_addr read pointer. */
|
||||||
|
x_len_bytes -= x_size_rx;
|
||||||
|
x_addr += x_size_rx;
|
||||||
|
}
|
||||||
|
PR;
|
||||||
|
return XSPI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void xspi_ip_write(uint32_t pc_wr_addr, uint32_t *pv_wr_buf, uint32_t ui_len)
|
||||||
|
{
|
||||||
|
|
||||||
|
uint32_t x_iteration = 0U, x_rem = 0U;
|
||||||
|
uint32_t x_size_tx = 0U, x_size_wm, temp_size;
|
||||||
|
uint32_t i = 0U, j = 0U;
|
||||||
|
uint32_t ui_data = 0U;
|
||||||
|
uint32_t x_addr, x_len_bytes;
|
||||||
|
|
||||||
|
|
||||||
|
x_size_wm = 8U; /* Default TX WaterMark level: 8 Bytes. */
|
||||||
|
x_addr = (uint32_t)pc_wr_addr;
|
||||||
|
x_len_bytes = ui_len;
|
||||||
|
VERBOSE("In func %s[%d] x_addr =0x%x xLen_bytes=%d\n",
|
||||||
|
__func__, __LINE__, x_addr, x_len_bytes);
|
||||||
|
|
||||||
|
while (x_len_bytes != 0U) {
|
||||||
|
|
||||||
|
x_size_tx = (x_len_bytes > FSPI_TX_IPBUF_SIZE) ?
|
||||||
|
FSPI_TX_IPBUF_SIZE : x_len_bytes;
|
||||||
|
|
||||||
|
/* IP Control Register0 - SF Address to be read */
|
||||||
|
fspi_writel(FSPI_IPCR0, x_addr);
|
||||||
|
INFO("In func %s[%d] x_addr =0x%x xLen_bytes=%d\n",
|
||||||
|
__func__, __LINE__, x_addr, x_len_bytes);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Fill TX FIFO's..
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
x_iteration = x_size_tx / x_size_wm;
|
||||||
|
for (i = 0U; i < x_iteration; i++) {
|
||||||
|
|
||||||
|
/* Ensure TX FIFO Watermark Available */
|
||||||
|
while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE_MASK) == 0)
|
||||||
|
;
|
||||||
|
|
||||||
|
|
||||||
|
/* Fill TxFIFO's ( upto watermark level) */
|
||||||
|
for (j = 0U; j < x_size_wm; j += 4U) {
|
||||||
|
memcpy(&ui_data, pv_wr_buf++, 4);
|
||||||
|
/* Write TX FIFO Data Register */
|
||||||
|
fspi_writel((FSPI_TFDR + j), ui_data);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear IP_TX_WATERMARK Event in INTR register */
|
||||||
|
/* Reset the FIFO Write pointer for next iteration */
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPTXWE);
|
||||||
|
}
|
||||||
|
|
||||||
|
x_rem = x_size_tx % x_size_wm;
|
||||||
|
|
||||||
|
if (x_rem != 0U) {
|
||||||
|
/* Wait for TXFIFO empty */
|
||||||
|
while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE))
|
||||||
|
;
|
||||||
|
|
||||||
|
temp_size = 0U;
|
||||||
|
j = 0U;
|
||||||
|
while (x_rem > 0U) {
|
||||||
|
ui_data = 0U;
|
||||||
|
temp_size = (x_rem < 4U) ? x_rem : 4U;
|
||||||
|
memcpy(&ui_data, pv_wr_buf++, temp_size);
|
||||||
|
INFO("%d ---> pv_wr_buf=0x%p\n", __LINE__, pv_wr_buf);
|
||||||
|
fspi_writel((FSPI_TFDR + j), ui_data);
|
||||||
|
x_rem -= temp_size;
|
||||||
|
j += 4U ; /* TODO: May not be needed*/
|
||||||
|
}
|
||||||
|
/* Clear IP_TX_WATERMARK Event in INTR register */
|
||||||
|
/* Reset FIFO's Write pointer for next iteration.*/
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPTXWE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* IP Control Register1 - SEQID_WRITE operation, Size */
|
||||||
|
fspi_writel(FSPI_IPCR1, (uint32_t)(FSPI_WRITE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | (uint16_t) x_size_tx);
|
||||||
|
/* Trigger IP Write Command */
|
||||||
|
fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
|
||||||
|
|
||||||
|
/* Wait for IP Write command done */
|
||||||
|
while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK))
|
||||||
|
;
|
||||||
|
|
||||||
|
/* Invalidate TX FIFOs & acknowledge IP_CMD_DONE event */
|
||||||
|
fspi_writel(FSPI_IPTXFCR, FSPI_IPTXFCR_CLR);
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
|
||||||
|
|
||||||
|
/* for next iteration */
|
||||||
|
x_len_bytes -= x_size_tx;
|
||||||
|
x_addr += x_size_tx;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
int xspi_write(uint32_t pc_wr_addr, void *pv_wr_buf, uint32_t ui_len)
|
||||||
|
{
|
||||||
|
|
||||||
|
uint32_t x_addr;
|
||||||
|
uint32_t x_page1_len = 0U, x_page_l_len = 0U;
|
||||||
|
uint32_t i, j = 0U;
|
||||||
|
void *buf = pv_wr_buf;
|
||||||
|
|
||||||
|
VERBOSE("\nIn func %s\n", __func__);
|
||||||
|
|
||||||
|
x_addr = (uint32_t)(pc_wr_addr);
|
||||||
|
if ((ui_len <= F_PAGE_256) && ((x_addr % F_PAGE_256) == 0)) {
|
||||||
|
x_page1_len = ui_len;
|
||||||
|
INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j);
|
||||||
|
} else if ((ui_len <= F_PAGE_256) && ((x_addr % F_PAGE_256) != 0)) {
|
||||||
|
x_page1_len = (F_PAGE_256 - (x_addr % F_PAGE_256));
|
||||||
|
if (ui_len > x_page1_len) {
|
||||||
|
x_page_l_len = (ui_len - x_page1_len) % F_PAGE_256;
|
||||||
|
} else {
|
||||||
|
x_page1_len = ui_len;
|
||||||
|
x_page_l_len = 0;
|
||||||
|
}
|
||||||
|
j = 0U;
|
||||||
|
INFO("%d 0x%x 0x%x\n", x_addr % F_PAGE_256, x_addr % F_PAGE_256, F_PAGE_256);
|
||||||
|
INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j);
|
||||||
|
} else if ((ui_len > F_PAGE_256) && ((x_addr % F_PAGE_256) == 0)) {
|
||||||
|
j = ui_len / F_PAGE_256;
|
||||||
|
x_page_l_len = ui_len % F_PAGE_256;
|
||||||
|
INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j);
|
||||||
|
} else if ((ui_len > F_PAGE_256) && ((x_addr % F_PAGE_256) != 0)) {
|
||||||
|
x_page1_len = (F_PAGE_256 - (x_addr % F_PAGE_256));
|
||||||
|
j = (ui_len - x_page1_len) / F_PAGE_256;
|
||||||
|
x_page_l_len = (ui_len - x_page1_len) % F_PAGE_256;
|
||||||
|
INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (x_page1_len != 0U) {
|
||||||
|
xspi_wren(x_addr);
|
||||||
|
xspi_ip_write(x_addr, (uint32_t *)buf, x_page1_len);
|
||||||
|
while (is_flash_busy())
|
||||||
|
;
|
||||||
|
INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n",
|
||||||
|
__LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr));
|
||||||
|
INFO("Initial Buf pv_wr_buf=%p, final Buf=%p\n", pv_wr_buf, buf);
|
||||||
|
x_addr += x_page1_len;
|
||||||
|
/* TODO What is buf start is not 4 aligned */
|
||||||
|
buf = buf + x_page1_len;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0U; i < j; i++) {
|
||||||
|
INFO("In for loop Buf pv_wr_buf=%p, final Buf=%p x_addr=0x%x offset_buf %d.\n",
|
||||||
|
pv_wr_buf, buf, x_addr, x_page1_len/4);
|
||||||
|
xspi_wren(x_addr);
|
||||||
|
xspi_ip_write(x_addr, (uint32_t *)buf, F_PAGE_256);
|
||||||
|
while (is_flash_busy())
|
||||||
|
;
|
||||||
|
INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n",
|
||||||
|
__LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr));
|
||||||
|
x_addr += F_PAGE_256;
|
||||||
|
/* TODO What is buf start is not 4 aligned */
|
||||||
|
buf = buf + F_PAGE_256;
|
||||||
|
INFO("Initial Buf pv_wr_buf=%p, final Buf=%p\n", pv_wr_buf, buf);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (x_page_l_len != 0U) {
|
||||||
|
INFO("%d Initial Buf pv_wr_buf=%p, final Buf=%p x_page_l_len=0x%x\n", __LINE__, pv_wr_buf, buf, x_page_l_len);
|
||||||
|
xspi_wren(x_addr);
|
||||||
|
xspi_ip_write(x_addr, (uint32_t *)buf, x_page_l_len);
|
||||||
|
while (is_flash_busy())
|
||||||
|
;
|
||||||
|
INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n",
|
||||||
|
__LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr));
|
||||||
|
}
|
||||||
|
|
||||||
|
VERBOSE("Now calling func call Invalidate%s\n", __func__);
|
||||||
|
fspi_ahb_invalidate();
|
||||||
|
return XSPI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
int xspi_wren(uint32_t pc_wr_addr)
|
||||||
|
{
|
||||||
|
VERBOSE("In func %s Addr=0x%x\n", __func__, pc_wr_addr);
|
||||||
|
|
||||||
|
fspi_writel(FSPI_IPTXFCR, FSPI_IPTXFCR_CLR);
|
||||||
|
|
||||||
|
fspi_writel(FSPI_IPCR0, (uint32_t)pc_wr_addr);
|
||||||
|
fspi_writel(FSPI_IPCR1, ((FSPI_WREN_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0));
|
||||||
|
fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
|
||||||
|
|
||||||
|
while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)
|
||||||
|
;
|
||||||
|
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
|
||||||
|
return XSPI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fspi_bbluk_er(void)
|
||||||
|
{
|
||||||
|
VERBOSE("In func %s\n", __func__);
|
||||||
|
fspi_writel(FSPI_IPCR0, 0x0);
|
||||||
|
fspi_writel(FSPI_IPCR1, ((FSPI_BE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 20));
|
||||||
|
fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
|
||||||
|
|
||||||
|
while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)
|
||||||
|
;
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fspi_RDSR(uint32_t *rxbuf, const void *p_addr, uint32_t size)
|
||||||
|
{
|
||||||
|
uint32_t iprxfcr = 0U;
|
||||||
|
uint32_t data = 0U;
|
||||||
|
|
||||||
|
iprxfcr = fspi_readl(FSPI_IPRXFCR);
|
||||||
|
/* IP RX FIFO would be read by processor */
|
||||||
|
iprxfcr = iprxfcr & (uint32_t)~FSPI_IPRXFCR_CLR;
|
||||||
|
/* Invalid data entries in IP RX FIFO */
|
||||||
|
iprxfcr = iprxfcr | FSPI_IPRXFCR_CLR;
|
||||||
|
fspi_writel(FSPI_IPRXFCR, iprxfcr);
|
||||||
|
|
||||||
|
fspi_writel(FSPI_IPCR0, (uintptr_t) p_addr);
|
||||||
|
fspi_writel(FSPI_IPCR1,
|
||||||
|
(uint32_t) ((FSPI_RDSR_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT)
|
||||||
|
| (uint16_t) size));
|
||||||
|
/* Trigger the command */
|
||||||
|
fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
|
||||||
|
/* Wait for command done */
|
||||||
|
while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)
|
||||||
|
;
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
|
||||||
|
|
||||||
|
data = fspi_readl(FSPI_RFDR);
|
||||||
|
memcpy(rxbuf, &data, size);
|
||||||
|
|
||||||
|
/* Rx FIFO invalidation needs to be done prior w1c of INTR.IPRXWA bit */
|
||||||
|
fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR);
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA_MASK);
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
bool is_flash_busy(void)
|
||||||
|
{
|
||||||
|
#define FSPI_ONE_BYTE 1
|
||||||
|
uint8_t data[4];
|
||||||
|
|
||||||
|
VERBOSE("In func %s\n\n", __func__);
|
||||||
|
fspi_RDSR((uint32_t *) data, 0, FSPI_ONE_BYTE);
|
||||||
|
|
||||||
|
return !!((uint32_t) data[0] & FSPI_NOR_SR_WIP_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
int xspi_bulk_erase(void)
|
||||||
|
{
|
||||||
|
VERBOSE("In func %s\n", __func__);
|
||||||
|
xspi_wren((uint32_t) 0x0);
|
||||||
|
fspi_bbluk_er();
|
||||||
|
while (is_flash_busy())
|
||||||
|
;
|
||||||
|
fspi_ahb_invalidate();
|
||||||
|
return XSPI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void fspi_sec_er(uint32_t pc_wr_addr)
|
||||||
|
{
|
||||||
|
uint32_t x_addr;
|
||||||
|
|
||||||
|
VERBOSE("In func %s\n", __func__);
|
||||||
|
x_addr = (uint32_t)(pc_wr_addr);
|
||||||
|
|
||||||
|
fspi_writel(FSPI_IPCR0, x_addr);
|
||||||
|
INFO("In [%s][%d] Erase address 0x%x\n", __func__, __LINE__, (x_addr));
|
||||||
|
#if CONFIG_FSPI_ERASE_4K
|
||||||
|
fspi_writel(FSPI_IPCR1, ((FSPI_4K_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0));
|
||||||
|
#else
|
||||||
|
fspi_writel(FSPI_IPCR1, ((FSPI_SE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0));
|
||||||
|
#endif
|
||||||
|
fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
|
||||||
|
|
||||||
|
while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) {
|
||||||
|
PRA("0x%x", fspi_readl(FSPI_INTR));
|
||||||
|
}
|
||||||
|
fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
int xspi_sector_erase(uint32_t pc_wr_addr, uint32_t ui_len)
|
||||||
|
{
|
||||||
|
uint32_t x_addr, x_len_bytes, i, num_sector = 0U;
|
||||||
|
|
||||||
|
VERBOSE("In func %s\n", __func__);
|
||||||
|
x_addr = (uint32_t)(pc_wr_addr);
|
||||||
|
if ((x_addr % F_SECTOR_ERASE_SZ) != 0) {
|
||||||
|
ERROR("!!! In func %s, unalinged start address can only be in multiples of 0x%x\n",
|
||||||
|
__func__, F_SECTOR_ERASE_SZ);
|
||||||
|
return -XSPI_ERASE_FAIL;
|
||||||
|
}
|
||||||
|
|
||||||
|
x_len_bytes = ui_len * 1;
|
||||||
|
if (x_len_bytes < F_SECTOR_ERASE_SZ) {
|
||||||
|
ERROR("!!! In func %s, Less than 1 sector can only be in multiples of 0x%x\n",
|
||||||
|
__func__, F_SECTOR_ERASE_SZ);
|
||||||
|
return -XSPI_ERASE_FAIL;
|
||||||
|
}
|
||||||
|
|
||||||
|
num_sector = x_len_bytes/F_SECTOR_ERASE_SZ;
|
||||||
|
num_sector += x_len_bytes % F_SECTOR_ERASE_SZ ? 1U : 0U;
|
||||||
|
INFO("F_SECTOR_ERASE_SZ: 0x%08x, num_sector: %d\n", F_SECTOR_ERASE_SZ, num_sector);
|
||||||
|
|
||||||
|
for (i = 0U; i < num_sector ; i++) {
|
||||||
|
xspi_wren(x_addr + (F_SECTOR_ERASE_SZ * i));
|
||||||
|
fspi_sec_er(x_addr + (F_SECTOR_ERASE_SZ * i));
|
||||||
|
while (is_flash_busy())
|
||||||
|
;
|
||||||
|
}
|
||||||
|
fspi_ahb_invalidate();
|
||||||
|
return XSPI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
__attribute__((unused)) static void fspi_delay_ms(uint32_t x)
|
||||||
|
{
|
||||||
|
volatile unsigned long ul_count;
|
||||||
|
|
||||||
|
for (ul_count = 0U; ul_count < (30U * x); ul_count++)
|
||||||
|
;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(DEBUG_FLEXSPI)
|
||||||
|
static void fspi_dump_regs(void)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
VERBOSE("\nRegisters Dump:\n");
|
||||||
|
VERBOSE("Flexspi: Register FSPI_MCR0(0x%x) = 0x%08x\n", FSPI_MCR0, fspi_readl(FSPI_MCR0));
|
||||||
|
VERBOSE("Flexspi: Register FSPI_MCR2(0x%x) = 0x%08x\n", FSPI_MCR2, fspi_readl(FSPI_MCR2));
|
||||||
|
VERBOSE("Flexspi: Register FSPI_DLL_A_CR(0x%x) = 0x%08x\n", FSPI_DLLACR, fspi_readl(FSPI_DLLACR));
|
||||||
|
VERBOSE("\n");
|
||||||
|
|
||||||
|
for (i = 0U; i < 8U; i++) {
|
||||||
|
VERBOSE("Flexspi: Register FSPI_AHBRX_BUF0CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF0CR0 + i * 4, fspi_readl((FSPI_AHBRX_BUF0CR0 + i * 4)));
|
||||||
|
}
|
||||||
|
VERBOSE("\n");
|
||||||
|
|
||||||
|
VERBOSE("Flexspi: Register FSPI_AHBRX_BUF7CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF7CR0, fspi_readl(FSPI_AHBRX_BUF7CR0));
|
||||||
|
VERBOSE("Flexspi: Register FSPI_AHB_CR(0x%x) \t = 0x%08x\n", FSPI_AHBCR, fspi_readl(FSPI_AHBCR));
|
||||||
|
VERBOSE("\n");
|
||||||
|
|
||||||
|
for (i = 0U; i < 4U; i++) {
|
||||||
|
VERBOSE("Flexspi: Register FSPI_FLSH_A1_CR2,(0x%x) = 0x%08x\n", FSPI_FLSHA1CR2 + i * 4, fspi_readl(FSPI_FLSHA1CR2 + i * 4));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int fspi_init(uint32_t base_reg_addr, uint32_t flash_start_addr)
|
||||||
|
{
|
||||||
|
uint32_t mcrx;
|
||||||
|
uint32_t flash_size;
|
||||||
|
|
||||||
|
if (fspi_base_reg_addr != 0U) {
|
||||||
|
INFO("FSPI is already initialized.\n");
|
||||||
|
return XSPI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
fspi_base_reg_addr = base_reg_addr;
|
||||||
|
fspi_flash_base_addr = flash_start_addr;
|
||||||
|
|
||||||
|
INFO("Flexspi driver: Version v1.0\n");
|
||||||
|
INFO("Flexspi: Default MCR0 = 0x%08x, before reset\n", fspi_readl(FSPI_MCR0));
|
||||||
|
VERBOSE("Flexspi: Resetting controller...\n");
|
||||||
|
|
||||||
|
/* Reset FlexSpi Controller */
|
||||||
|
fspi_writel(FSPI_MCR0, FSPI_MCR0_SWRST);
|
||||||
|
while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST))
|
||||||
|
; /* FSPI_MCR0_SWRESET_MASK */
|
||||||
|
|
||||||
|
|
||||||
|
/* Disable Controller Module before programming its registersi, especially MCR0 (Master Control Register0) */
|
||||||
|
fspi_MDIS(1);
|
||||||
|
/*
|
||||||
|
* Program MCR0 with default values, AHB Timeout(0xff), IP Timeout(0xff). {FSPI_MCR0- 0xFFFF0000}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Timeout wait cycle for AHB command grant */
|
||||||
|
mcrx = fspi_readl(FSPI_MCR0);
|
||||||
|
mcrx |= (uint32_t)((FSPI_MAX_TIMEOUT_AHBCMD << FSPI_MCR0_AHBGRANTWAIT_SHIFT) & (FSPI_MCR0_AHBGRANTWAIT_MASK));
|
||||||
|
|
||||||
|
/* Time out wait cycle for IP command grant*/
|
||||||
|
mcrx |= (uint32_t) (FSPI_MAX_TIMEOUT_IPCMD << FSPI_MCR0_IPGRANTWAIT_SHIFT) & (FSPI_MCR0_IPGRANTWAIT_MASK);
|
||||||
|
|
||||||
|
/* TODO why BE64 set BE32*/
|
||||||
|
mcrx |= (uint32_t) (FSPI_ENDCFG_LE64 << FSPI_MCR0_ENDCFG_SHIFT) & FSPI_MCR0_ENDCFG_MASK;
|
||||||
|
|
||||||
|
fspi_writel(FSPI_MCR0, mcrx);
|
||||||
|
|
||||||
|
/* Reset the DLL register to default value */
|
||||||
|
fspi_writel(FSPI_DLLACR, FSPI_DLLACR_OVRDEN);
|
||||||
|
fspi_writel(FSPI_DLLBCR, FSPI_DLLBCR_OVRDEN);
|
||||||
|
|
||||||
|
#if ERRATA_FLASH_A050272 /* ERRATA DLL */
|
||||||
|
for (uint8_t delay = 100U; delay > 0U; delay--) {
|
||||||
|
__asm__ volatile ("nop");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure flash control registers for different chip select */
|
||||||
|
flash_size = (F_FLASH_SIZE_BYTES * FLASH_NUM) / FSPI_BYTES_PER_KBYTES;
|
||||||
|
fspi_writel(FSPI_FLSHA1CR0, flash_size);
|
||||||
|
fspi_writel(FSPI_FLSHA2CR0, 0U);
|
||||||
|
fspi_writel(FSPI_FLSHB1CR0, 0U);
|
||||||
|
fspi_writel(FSPI_FLSHB2CR0, 0U);
|
||||||
|
|
||||||
|
#if defined(CONFIG_FSPI_AHB)
|
||||||
|
fspi_init_ahb();
|
||||||
|
#endif
|
||||||
|
/* RE-Enable Controller Module */
|
||||||
|
fspi_MDIS(0);
|
||||||
|
INFO("Flexspi: After MCR0 = 0x%08x,\n", fspi_readl(FSPI_MCR0));
|
||||||
|
fspi_setup_LUT();
|
||||||
|
|
||||||
|
/* Dump of all registers, ensure controller not disabled anymore*/
|
||||||
|
#if defined(DEBUG_FLEXSPI)
|
||||||
|
fspi_dump_regs();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
INFO("Flexspi: Init done!!\n");
|
||||||
|
|
||||||
|
#if DEBUG_FLEXSPI
|
||||||
|
|
||||||
|
uint32_t xspi_addr = SZ_57M;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Second argument of fspi_test is the size of buffer(s) passed
|
||||||
|
* to the function.
|
||||||
|
* SIZE_BUFFER defined in test_fspi.c is kept large enough to
|
||||||
|
* accommodate variety of sizes for regressive tests.
|
||||||
|
*/
|
||||||
|
fspi_test(xspi_addr, 0x40, 0);
|
||||||
|
fspi_test(xspi_addr, 0x15, 2);
|
||||||
|
fspi_test(xspi_addr, 0x80, 0);
|
||||||
|
fspi_test(xspi_addr, 0x81, 0);
|
||||||
|
fspi_test(xspi_addr, 0x79, 3);
|
||||||
|
|
||||||
|
fspi_test(xspi_addr + 0x11, 0x15, 0);
|
||||||
|
fspi_test(xspi_addr + 0x11, 0x40, 0);
|
||||||
|
fspi_test(xspi_addr + 0xff, 0x40, 1);
|
||||||
|
fspi_test(xspi_addr + 0x25, 0x81, 2);
|
||||||
|
fspi_test(xspi_addr + 0xef, 0x6f, 3);
|
||||||
|
|
||||||
|
fspi_test((xspi_addr - F_SECTOR_ERASE_SZ), 0x229, 0);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return XSPI_SUCCESS;
|
||||||
|
}
|
||||||
385
drivers/nxp/flexspi/nor/fspi.h
Normal file
385
drivers/nxp/flexspi/nor/fspi.h
Normal file
|
|
@ -0,0 +1,385 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2021 NXP
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*
|
||||||
|
* FlexSpi Registers & Bits definition.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef FSPI_H
|
||||||
|
#define FSPI_H
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLER__
|
||||||
|
#include <lib/mmio.h>
|
||||||
|
|
||||||
|
#ifdef NXP_FSPI_BE
|
||||||
|
#define fspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
|
||||||
|
#define fspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
|
||||||
|
#elif defined(NXP_FSPI_LE)
|
||||||
|
#define fspi_in32(a) mmio_read_32((uintptr_t)(a))
|
||||||
|
#define fspi_out32(a, v) mmio_write_32((uintptr_t)(a), v)
|
||||||
|
#else
|
||||||
|
#error Please define FSPI register endianness
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* All LE so not swap needed */
|
||||||
|
#define FSPI_IPDATA_SWAP 0U
|
||||||
|
#define FSPI_AHBDATA_SWAP 0U
|
||||||
|
|
||||||
|
#define CONFIG_FSPI_FASTREAD 1U
|
||||||
|
|
||||||
|
#define FSPI_BYTES_PER_KBYTES 0x400U
|
||||||
|
#define FLASH_NUM 1U
|
||||||
|
|
||||||
|
#define FSPI_READ_SEQ_ID 0U
|
||||||
|
#define FSPI_WREN_SEQ_ID 1U
|
||||||
|
#define FSPI_WRITE_SEQ_ID 2U
|
||||||
|
#define FSPI_SE_SEQ_ID 3U
|
||||||
|
#define FSPI_RDSR_SEQ_ID 4U
|
||||||
|
#define FSPI_BE_SEQ_ID 5U
|
||||||
|
#define FSPI_FASTREAD_SEQ_ID 6U
|
||||||
|
#define FSPI_4K_SEQ_ID 7U
|
||||||
|
|
||||||
|
/*
|
||||||
|
* LUT register layout:
|
||||||
|
*
|
||||||
|
* ---------------------------------------------------
|
||||||
|
* | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
|
||||||
|
* ---------------------------------------------------
|
||||||
|
*
|
||||||
|
* INSTR_SHIFT- 10, PAD_SHIFT - 8, OPRND_SHIFT -0
|
||||||
|
*/
|
||||||
|
#define FSPI_INSTR_OPRND0_SHIFT 0
|
||||||
|
#define FSPI_INSTR_OPRND0(x) (x << FSPI_INSTR_OPRND0_SHIFT)
|
||||||
|
#define FSPI_INSTR_PAD0_SHIFT 8
|
||||||
|
#define FSPI_INSTR_PAD0(x) ((x) << FSPI_INSTR_PAD0_SHIFT)
|
||||||
|
#define FSPI_INSTR_OPCODE0_SHIFT 10
|
||||||
|
#define FSPI_INSTR_OPCODE0(x) ((x) << FSPI_INSTR_OPCODE0_SHIFT)
|
||||||
|
#define FSPI_INSTR_OPRND1_SHIFT 16
|
||||||
|
#define FSPI_INSTR_OPRND1(x) ((x) << FSPI_INSTR_OPRND1_SHIFT)
|
||||||
|
#define FSPI_INSTR_PAD1_SHIFT 24
|
||||||
|
#define FSPI_INSTR_PAD1(x) ((x) << FSPI_INSTR_PAD1_SHIFT)
|
||||||
|
#define FSPI_INSTR_OPCODE1_SHIFT 26
|
||||||
|
#define FSPI_INSTR_OPCODE1(x) ((x) << FSPI_INSTR_OPCODE1_SHIFT)
|
||||||
|
|
||||||
|
/* Instruction set for the LUT register. */
|
||||||
|
#define LUT_STOP 0x00
|
||||||
|
#define LUT_CMD 0x01
|
||||||
|
#define LUT_ADDR 0x02
|
||||||
|
#define LUT_CADDR_SDR 0x03
|
||||||
|
#define LUT_MODE 0x04
|
||||||
|
#define LUT_MODE2 0x05
|
||||||
|
#define LUT_MODE4 0x06
|
||||||
|
#define LUT_MODE8 0x07
|
||||||
|
#define LUT_NXP_WRITE 0x08
|
||||||
|
#define LUT_NXP_READ 0x09
|
||||||
|
|
||||||
|
#define LUT_LEARN_SDR 0x0A
|
||||||
|
#define LUT_DATSZ_SDR 0x0B
|
||||||
|
#define LUT_DUMMY 0x0C
|
||||||
|
#define LUT_DUMMY_RWDS_SDR 0x0D
|
||||||
|
#define LUT_JMP_ON_CS 0x1F
|
||||||
|
#define LUT_CMD_DDR 0x21
|
||||||
|
#define LUT_ADDR_DDR 0x22
|
||||||
|
#define LUT_CADDR_DDR 0x23
|
||||||
|
#define LUT_MODE_DDR 0x24
|
||||||
|
#define LUT_MODE2_DDR 0x25
|
||||||
|
#define LUT_MODE4_DDR 0x26
|
||||||
|
#define LUT_MODE8_DDR 0x27
|
||||||
|
#define LUT_WRITE_DDR 0x28
|
||||||
|
#define LUT_READ_DDR 0x29
|
||||||
|
#define LUT_LEARN_DDR 0x2A
|
||||||
|
#define LUT_DATSZ_DDR 0x2B
|
||||||
|
#define LUT_DUMMY_DDR 0x2C
|
||||||
|
#define LUT_DUMMY_RWDS_DDR 0x2D
|
||||||
|
|
||||||
|
#define FSPI_NOR_CMD_READ 0x03
|
||||||
|
#define FSPI_NOR_CMD_READ_4B 0x13
|
||||||
|
#define FSPI_NOR_CMD_FASTREAD 0x0b
|
||||||
|
#define FSPI_NOR_CMD_FASTREAD_4B 0x0c
|
||||||
|
#define FSPI_NOR_CMD_PP 0x02
|
||||||
|
#define FSPI_NOR_CMD_PP_4B 0x12
|
||||||
|
#define FSPI_NOR_CMD_WREN 0x06
|
||||||
|
#define FSPI_NOR_CMD_SE_64K 0xd8
|
||||||
|
#define FSPI_NOR_CMD_SE_64K_4B 0xdc
|
||||||
|
#define FSPI_NOR_CMD_SE_4K 0x20
|
||||||
|
#define FSPI_NOR_CMD_SE_4K_4B 0x21
|
||||||
|
#define FSPI_NOR_CMD_BE 0x60
|
||||||
|
#define FSPI_NOR_CMD_RDSR 0x05
|
||||||
|
#define FSPI_NOR_CMD_WREN_STOP 0x04
|
||||||
|
|
||||||
|
#define FSPI_LUT_STOP 0x00
|
||||||
|
#define FSPI_LUT_CMD 0x01
|
||||||
|
#define FSPI_LUT_ADDR 0x02
|
||||||
|
|
||||||
|
#define FSPI_LUT_PAD1 0
|
||||||
|
#define FSPI_LUT_PAD2 1
|
||||||
|
#define FSPI_LUT_PAD4 2
|
||||||
|
#define FSPI_LUT_PAD8 3
|
||||||
|
|
||||||
|
#define FSPI_LUT_ADDR24BIT 0x18
|
||||||
|
#define FSPI_LUT_ADDR32BIT 0x20
|
||||||
|
|
||||||
|
#define FSPI_LUT_WRITE 0x08
|
||||||
|
#define FSPI_LUT_READ 0x09
|
||||||
|
#define FSPI_DUMMY_SDR 0x0c
|
||||||
|
|
||||||
|
/* TODO Check size if functional*/
|
||||||
|
#define FSPI_RX_IPBUF_SIZE 0x200 /* 64*64 bits */
|
||||||
|
#define FSPI_TX_IPBUF_SIZE 0x400 /* 128*64 bits */
|
||||||
|
|
||||||
|
#define FSPI_RX_MAX_AHBBUF_SIZE 0x800 /* 256 * 64bits */
|
||||||
|
#define FSPI_TX_MAX_AHBBUF_SIZE 0x40 /* 8 * 64bits */
|
||||||
|
|
||||||
|
#define FSPI_LUTREG_OFFSET 0x200ul
|
||||||
|
|
||||||
|
#define FSPI_MAX_TIMEOUT_AHBCMD 0xFFU
|
||||||
|
#define FSPI_MAX_TIMEOUT_IPCMD 0xFF
|
||||||
|
#define FSPI_SER_CLK_DIV 0x04
|
||||||
|
#define FSPI_HSEN 0
|
||||||
|
#define FSPI_ENDCFG_BE64 0x01
|
||||||
|
#define FSPI_ENDCFG_BE32 0x03
|
||||||
|
#define FSPI_ENDCFG_LE32 0x02
|
||||||
|
#define FSPI_ENDCFG_LE64 0x0
|
||||||
|
|
||||||
|
#define MASK_24BIT_ADDRESS 0x00ffffff
|
||||||
|
#define MASK_32BIT_ADDRESS 0xffffffff
|
||||||
|
|
||||||
|
/* Registers used by the driver */
|
||||||
|
#define FSPI_MCR0 0x0ul
|
||||||
|
#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
|
||||||
|
#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
|
||||||
|
#define FSPI_MCR0_LEARN_EN BIT(15)
|
||||||
|
#define FSPI_MCR0_SCRFRUN_EN BIT(14)
|
||||||
|
#define FSPI_MCR0_OCTCOMB_EN BIT(13)
|
||||||
|
#define FSPI_MCR0_DOZE_EN BIT(12)
|
||||||
|
#define FSPI_MCR0_HSEN BIT(11)
|
||||||
|
#define FSPI_MCR0_SERCLKDIV BIT(8)
|
||||||
|
#define FSPI_MCR0_ATDF_EN BIT(7)
|
||||||
|
#define FSPI_MCR0_ARDF_EN BIT(6)
|
||||||
|
#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
|
||||||
|
#define FSPI_MCR0_END_CFG(x) ((x) << 2)
|
||||||
|
#define FSPI_MCR0_MDIS BIT(1)
|
||||||
|
#define FSPI_MCR0_SWRST BIT(0)
|
||||||
|
|
||||||
|
#define FSPI_MCR0_AHBGRANTWAIT_SHIFT 24
|
||||||
|
#define FSPI_MCR0_AHBGRANTWAIT_MASK (0xFFU << FSPI_MCR0_AHBGRANTWAIT_SHIFT)
|
||||||
|
#define FSPI_MCR0_IPGRANTWAIT_SHIFT 16
|
||||||
|
#define FSPI_MCR0_IPGRANTWAIT_MASK (0xFF << FSPI_MCR0_IPGRANTWAIT_SHIFT)
|
||||||
|
#define FSPI_MCR0_HSEN_SHIFT 11
|
||||||
|
#define FSPI_MCR0_HSEN_MASK (1 << FSPI_MCR0_HSEN_SHIFT)
|
||||||
|
#define FSPI_MCR0_SERCLKDIV_SHIFT 8
|
||||||
|
#define FSPI_MCR0_SERCLKDIV_MASK (7 << FSPI_MCR0_SERCLKDIV_SHIFT)
|
||||||
|
#define FSPI_MCR0_ENDCFG_SHIFT 2
|
||||||
|
#define FSPI_MCR0_ENDCFG_MASK (3 << FSPI_MCR0_ENDCFG_SHIFT)
|
||||||
|
#define FSPI_MCR0_RXCLKSRC_SHIFT 4
|
||||||
|
#define FSPI_MCR0_RXCLKSRC_MASK (3 << FSPI_MCR0_RXCLKSRC_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_MCR1 0x04
|
||||||
|
#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
|
||||||
|
#define FSPI_MCR1_AHB_TIMEOUT(x) (x)
|
||||||
|
|
||||||
|
#define FSPI_MCR2 0x08
|
||||||
|
#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
|
||||||
|
#define FSPI_MCR2_SAMEDEVICEEN BIT(15)
|
||||||
|
#define FSPI_MCR2_CLRLRPHS BIT(14)
|
||||||
|
#define FSPI_MCR2_ABRDATSZ BIT(8)
|
||||||
|
#define FSPI_MCR2_ABRLEARN BIT(7)
|
||||||
|
#define FSPI_MCR2_ABR_READ BIT(6)
|
||||||
|
#define FSPI_MCR2_ABRWRITE BIT(5)
|
||||||
|
#define FSPI_MCR2_ABRDUMMY BIT(4)
|
||||||
|
#define FSPI_MCR2_ABR_MODE BIT(3)
|
||||||
|
#define FSPI_MCR2_ABRCADDR BIT(2)
|
||||||
|
#define FSPI_MCR2_ABRRADDR BIT(1)
|
||||||
|
#define FSPI_MCR2_ABR_CMD BIT(0)
|
||||||
|
|
||||||
|
#define FSPI_AHBCR 0x0c
|
||||||
|
#define FSPI_AHBCR_RDADDROPT BIT(6)
|
||||||
|
#define FSPI_AHBCR_PREF_EN BIT(5)
|
||||||
|
#define FSPI_AHBCR_BUFF_EN BIT(4)
|
||||||
|
#define FSPI_AHBCR_CACH_EN BIT(3)
|
||||||
|
#define FSPI_AHBCR_CLRTXBUF BIT(2)
|
||||||
|
#define FSPI_AHBCR_CLRRXBUF BIT(1)
|
||||||
|
#define FSPI_AHBCR_PAR_EN BIT(0)
|
||||||
|
|
||||||
|
#define FSPI_INTEN 0x10
|
||||||
|
#define FSPI_INTEN_SCLKSBWR BIT(9)
|
||||||
|
#define FSPI_INTEN_SCLKSBRD BIT(8)
|
||||||
|
#define FSPI_INTEN_DATALRNFL BIT(7)
|
||||||
|
#define FSPI_INTEN_IPTXWE BIT(6)
|
||||||
|
#define FSPI_INTEN_IPRXWA BIT(5)
|
||||||
|
#define FSPI_INTEN_AHBCMDERR BIT(4)
|
||||||
|
#define FSPI_INTEN_IPCMDERR BIT(3)
|
||||||
|
#define FSPI_INTEN_AHBCMDGE BIT(2)
|
||||||
|
#define FSPI_INTEN_IPCMDGE BIT(1)
|
||||||
|
#define FSPI_INTEN_IPCMDDONE BIT(0)
|
||||||
|
|
||||||
|
#define FSPI_INTR 0x14
|
||||||
|
#define FSPI_INTR_SCLKSBWR BIT(9)
|
||||||
|
#define FSPI_INTR_SCLKSBRD BIT(8)
|
||||||
|
#define FSPI_INTR_DATALRNFL BIT(7)
|
||||||
|
#define FSPI_INTR_IPTXWE BIT(6)
|
||||||
|
#define FSPI_INTR_IPRXWA BIT(5)
|
||||||
|
#define FSPI_INTR_AHBCMDERR BIT(4)
|
||||||
|
#define FSPI_INTR_IPCMDERR BIT(3)
|
||||||
|
#define FSPI_INTR_AHBCMDGE BIT(2)
|
||||||
|
#define FSPI_INTR_IPCMDGE BIT(1)
|
||||||
|
#define FSPI_INTR_IPCMDDONE BIT(0)
|
||||||
|
|
||||||
|
#define FSPI_LUTKEY 0x18
|
||||||
|
#define FSPI_LUTKEY_VALUE 0x5AF05AF0
|
||||||
|
|
||||||
|
#define FSPI_LCKCR 0x1C
|
||||||
|
|
||||||
|
#define FSPI_LCKER_LOCK 0x1
|
||||||
|
#define FSPI_LCKER_UNLOCK 0x2
|
||||||
|
|
||||||
|
#define FSPI_BUFXCR_INVALID_MSTRID 0xE
|
||||||
|
#define FSPI_AHBRX_BUF0CR0 0x20
|
||||||
|
#define FSPI_AHBRX_BUF1CR0 0x24
|
||||||
|
#define FSPI_AHBRX_BUF2CR0 0x28
|
||||||
|
#define FSPI_AHBRX_BUF3CR0 0x2C
|
||||||
|
#define FSPI_AHBRX_BUF4CR0 0x30
|
||||||
|
#define FSPI_AHBRX_BUF5CR0 0x34
|
||||||
|
#define FSPI_AHBRX_BUF6CR0 0x38
|
||||||
|
#define FSPI_AHBRX_BUF7CR0 0x3C
|
||||||
|
|
||||||
|
#define FSPI_AHBRXBUF0CR7_PREF BIT(31)
|
||||||
|
|
||||||
|
#define FSPI_AHBRX_BUF0CR1 0x40
|
||||||
|
#define FSPI_AHBRX_BUF1CR1 0x44
|
||||||
|
#define FSPI_AHBRX_BUF2CR1 0x48
|
||||||
|
#define FSPI_AHBRX_BUF3CR1 0x4C
|
||||||
|
#define FSPI_AHBRX_BUF4CR1 0x50
|
||||||
|
#define FSPI_AHBRX_BUF5CR1 0x54
|
||||||
|
#define FSPI_AHBRX_BUF6CR1 0x58
|
||||||
|
#define FSPI_AHBRX_BUF7CR1 0x5C
|
||||||
|
|
||||||
|
#define FSPI_FLSHA1CR0 0x60
|
||||||
|
#define FSPI_FLSHA2CR0 0x64
|
||||||
|
#define FSPI_FLSHB1CR0 0x68
|
||||||
|
#define FSPI_FLSHB2CR0 0x6C
|
||||||
|
#define FSPI_FLSHXCR0_SZ_KB 10
|
||||||
|
#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
|
||||||
|
|
||||||
|
#define FSPI_FLSHA1CR1 0x70
|
||||||
|
#define FSPI_FLSHA2CR1 0x74
|
||||||
|
#define FSPI_FLSHB1CR1 0x78
|
||||||
|
#define FSPI_FLSHB2CR1 0x7C
|
||||||
|
#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
|
||||||
|
#define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
|
||||||
|
#define FSPI_FLSHXCR1_WA BIT(10)
|
||||||
|
#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
|
||||||
|
#define FSPI_FLSHXCR1_TCSS(x) (x)
|
||||||
|
|
||||||
|
#define FSPI_FLSHXCR1_TCSH_SHIFT 5
|
||||||
|
#define FSPI_FLSHXCR1_TCSH_MASK (0x1F << FSPI_FLSHXCR1_TCSH_SHIFT)
|
||||||
|
#define FSPI_FLSHXCR1_TCSS_SHIFT 0
|
||||||
|
#define FSPI_FLSHXCR1_TCSS_MASK (0x1F << FSPI_FLSHXCR1_TCSS_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_FLSHA1CR2 0x80
|
||||||
|
#define FSPI_FLSHA2CR2 0x84
|
||||||
|
#define FSPI_FLSHB1CR2 0x88
|
||||||
|
#define FSPI_FLSHB2CR2 0x8C
|
||||||
|
#define FSPI_FLSHXCR2_CLRINSP BIT(24)
|
||||||
|
#define FSPI_FLSHXCR2_AWRWAIT BIT(16)
|
||||||
|
#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
|
||||||
|
#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
|
||||||
|
#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
|
||||||
|
#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
|
||||||
|
|
||||||
|
#define FSPI_IPCR0 0xA0
|
||||||
|
|
||||||
|
#define FSPI_IPCR1 0xA4
|
||||||
|
#define FSPI_IPCR1_IPAREN BIT(31)
|
||||||
|
#define FSPI_IPCR1_SEQNUM_SHIFT 24
|
||||||
|
#define FSPI_IPCR1_SEQID_SHIFT 16
|
||||||
|
#define FSPI_IPCR1_IDATSZ(x) (x)
|
||||||
|
|
||||||
|
#define FSPI_IPCMD 0xB0
|
||||||
|
#define FSPI_IPCMD_TRG BIT(0)
|
||||||
|
|
||||||
|
|
||||||
|
/* IP Command Register */
|
||||||
|
#define FSPI_IPCMD_TRG_SHIFT 0
|
||||||
|
#define FSPI_IPCMD_TRG_MASK (1 << FSPI_IPCMD_TRG_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_INTR_IPRXWA_SHIFT 5
|
||||||
|
#define FSPI_INTR_IPRXWA_MASK (1 << FSPI_INTR_IPRXWA_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_INTR_IPCMDDONE_SHIFT 0
|
||||||
|
#define FSPI_INTR_IPCMDDONE_MASK (1 << FSPI_INTR_IPCMDDONE_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_INTR_IPTXWE_SHIFT 6
|
||||||
|
#define FSPI_INTR_IPTXWE_MASK (1 << FSPI_INTR_IPTXWE_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_IPTXFSTS_FILL_SHIFT 0
|
||||||
|
#define FSPI_IPTXFSTS_FILL_MASK (0xFF << FSPI_IPTXFSTS_FILL_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_IPCR1_ISEQID_SHIFT 16
|
||||||
|
#define FSPI_IPCR1_ISEQID_MASK (0x1F << FSPI_IPCR1_ISEQID_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_IPRXFSTS_FILL_SHIFT 0
|
||||||
|
#define FSPI_IPRXFSTS_FILL_MASK (0xFF << FSPI_IPRXFSTS_FILL_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_DLPR 0xB4
|
||||||
|
|
||||||
|
#define FSPI_IPRXFCR 0xB8
|
||||||
|
#define FSPI_IPRXFCR_CLR BIT(0)
|
||||||
|
#define FSPI_IPRXFCR_DMA_EN BIT(1)
|
||||||
|
#define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
|
||||||
|
|
||||||
|
#define FSPI_IPTXFCR 0xBC
|
||||||
|
#define FSPI_IPTXFCR_CLR BIT(0)
|
||||||
|
#define FSPI_IPTXFCR_DMA_EN BIT(1)
|
||||||
|
#define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
|
||||||
|
|
||||||
|
#define FSPI_DLLACR 0xC0
|
||||||
|
#define FSPI_DLLACR_OVRDEN BIT(8)
|
||||||
|
|
||||||
|
#define FSPI_DLLBCR 0xC4
|
||||||
|
#define FSPI_DLLBCR_OVRDEN BIT(8)
|
||||||
|
|
||||||
|
#define FSPI_STS0 0xE0
|
||||||
|
#define FSPI_STS0_DLPHB(x) ((x) << 8)
|
||||||
|
#define FSPI_STS0_DLPHA(x) ((x) << 4)
|
||||||
|
#define FSPI_STS0_CMD_SRC(x) ((x) << 2)
|
||||||
|
#define FSPI_STS0_ARB_IDLE BIT(1)
|
||||||
|
#define FSPI_STS0_SEQ_IDLE BIT(0)
|
||||||
|
|
||||||
|
#define FSPI_STS1 0xE4
|
||||||
|
#define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
|
||||||
|
#define FSPI_STS1_IP_ERRID(x) ((x) << 16)
|
||||||
|
#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
|
||||||
|
#define FSPI_STS1_AHB_ERRID(x) (x)
|
||||||
|
|
||||||
|
#define FSPI_AHBSPNST 0xEC
|
||||||
|
#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
|
||||||
|
#define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
|
||||||
|
#define FSPI_AHBSPNST_ACTIVE BIT(0)
|
||||||
|
|
||||||
|
#define FSPI_IPRXFSTS 0xF0
|
||||||
|
#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
|
||||||
|
#define FSPI_IPRXFSTS_FILL(x) (x)
|
||||||
|
|
||||||
|
#define FSPI_IPTXFSTS 0xF4
|
||||||
|
#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
|
||||||
|
#define FSPI_IPTXFSTS_FILL(x) (x)
|
||||||
|
|
||||||
|
#define FSPI_NOR_SR_WIP_SHIFT (0)
|
||||||
|
#define FSPI_NOR_SR_WIP_MASK (1 << FSPI_NOR_SR_WIP_SHIFT)
|
||||||
|
|
||||||
|
#define FSPI_RFDR 0x100
|
||||||
|
#define FSPI_TFDR 0x180
|
||||||
|
|
||||||
|
#define FSPI_LUT_BASE 0x200
|
||||||
|
#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
|
||||||
|
#define FSPI_LUT_REG(idx) \
|
||||||
|
(FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
|
||||||
|
|
||||||
|
/* register map end */
|
||||||
|
|
||||||
|
#endif
|
||||||
91
drivers/nxp/flexspi/nor/test_fspi.c
Normal file
91
drivers/nxp/flexspi/nor/test_fspi.c
Normal file
|
|
@ -0,0 +1,91 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2021 NXP
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
|
||||||
|
#include <common/debug.h>
|
||||||
|
#include <flash_info.h>
|
||||||
|
#include "fspi.h"
|
||||||
|
#include <fspi_api.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The macros are defined to be used as test vector for testing fspi.
|
||||||
|
*/
|
||||||
|
#define SIZE_BUFFER 0x250
|
||||||
|
|
||||||
|
/*
|
||||||
|
* You may choose fspi_swap based on core endianness and flexspi IP/AHB
|
||||||
|
* buffer endianness set in MCR.
|
||||||
|
*/
|
||||||
|
#define fspi_swap32(A) (A)
|
||||||
|
|
||||||
|
void fspi_test(uint32_t fspi_test_addr, uint32_t size, int extra)
|
||||||
|
{
|
||||||
|
uint32_t buffer[SIZE_BUFFER];
|
||||||
|
uint32_t count = 1;
|
||||||
|
uint32_t failed, i;
|
||||||
|
|
||||||
|
NOTICE("-------------------------- %d----------------------------------\n", count++);
|
||||||
|
INFO("Sector Erase size: 0x%08x, size: %d\n", F_SECTOR_ERASE_SZ, size);
|
||||||
|
/* Test Sector Erase */
|
||||||
|
xspi_sector_erase(fspi_test_addr - fspi_test_addr % F_SECTOR_ERASE_SZ,
|
||||||
|
F_SECTOR_ERASE_SZ);
|
||||||
|
|
||||||
|
/* Test Erased data using IP read */
|
||||||
|
xspi_ip_read((fspi_test_addr), buffer, size * 4);
|
||||||
|
|
||||||
|
failed = 0;
|
||||||
|
for (i = 0; i < size; i++)
|
||||||
|
if (fspi_swap32(0xffffffff) != buffer[i]) {
|
||||||
|
failed = 1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (failed == 0) {
|
||||||
|
NOTICE("[%d]: Success Erase: data in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]);
|
||||||
|
} else {
|
||||||
|
ERROR("Erase: Failed -->xxx with buffer[%d]=0x%08x\n", i, buffer[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < SIZE_BUFFER; i++)
|
||||||
|
buffer[i] = 0x12345678;
|
||||||
|
|
||||||
|
/* Write data from buffer to flash */
|
||||||
|
xspi_write(fspi_test_addr, (void *)buffer, (size * 4 + extra));
|
||||||
|
/* Check written data using IP read */
|
||||||
|
xspi_ip_read(fspi_test_addr, buffer, (size * 4 + extra));
|
||||||
|
failed = 0;
|
||||||
|
for (i = 0; i < size; i++)
|
||||||
|
if (fspi_swap32(0x12345678) != buffer[i]) {
|
||||||
|
failed = 1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (failed == 0) {
|
||||||
|
NOTICE("[%d]: Success IpWrite with IP READ in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]);
|
||||||
|
} else {
|
||||||
|
ERROR("Write: Failed -->xxxx with IP READ in buffer[%d]=0x%08x\n", i, buffer[i]);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* xspi_read may use AHB read */
|
||||||
|
xspi_read((fspi_test_addr), buffer, (size * 4 + extra));
|
||||||
|
failed = 0;
|
||||||
|
for (i = 0; i < size; i++)
|
||||||
|
if (fspi_swap32(0x12345678) != buffer[i]) {
|
||||||
|
failed = 1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (failed == 0) {
|
||||||
|
NOTICE("[%d]: Success IpWrite with AHB OR IP READ on buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]);
|
||||||
|
} else {
|
||||||
|
ERROR("Write: Failed -->xxxx with AHB READ on buffer[%d]=0x%08x\n", i, buffer[i]);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
61
include/drivers/nxp/flexspi/flash_info.h
Normal file
61
include/drivers/nxp/flexspi/flash_info.h
Normal file
|
|
@ -0,0 +1,61 @@
|
||||||
|
// SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
/*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @Flash info
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#ifndef FLASH_INFO_H
|
||||||
|
#define FLASH_INFO_H
|
||||||
|
|
||||||
|
#define SZ_16M_BYTES 0x1000000U
|
||||||
|
|
||||||
|
#if defined(CONFIG_MT25QU512A)
|
||||||
|
#define F_SECTOR_64K 0x10000U
|
||||||
|
#define F_PAGE_256 0x100U
|
||||||
|
#define F_SECTOR_4K 0x1000U
|
||||||
|
#define F_FLASH_SIZE_BYTES 0x4000000U
|
||||||
|
#define F_SECTOR_ERASE_SZ F_SECTOR_64K
|
||||||
|
#ifdef CONFIG_FSPI_4K_ERASE
|
||||||
|
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined(CONFIG_MX25U25645G)
|
||||||
|
#define F_SECTOR_64K 0x10000U
|
||||||
|
#define F_PAGE_256 0x100U
|
||||||
|
#define F_SECTOR_4K 0x1000U
|
||||||
|
#define F_FLASH_SIZE_BYTES 0x2000000U
|
||||||
|
#define F_SECTOR_ERASE_SZ F_SECTOR_64K
|
||||||
|
#ifdef CONFIG_FSPI_4K_ERASE
|
||||||
|
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined(CONFIG_MX25U51245G)
|
||||||
|
#define F_SECTOR_64K 0x10000U
|
||||||
|
#define F_PAGE_256 0x100U
|
||||||
|
#define F_SECTOR_4K 0x1000U
|
||||||
|
#define F_FLASH_SIZE_BYTES 0x4000000U
|
||||||
|
#define F_SECTOR_ERASE_SZ F_SECTOR_64K
|
||||||
|
#ifdef CONFIG_FSPI_4K_ERASE
|
||||||
|
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined(CONFIG_MT35XU512A)
|
||||||
|
#define F_SECTOR_128K 0x20000U
|
||||||
|
#define F_SECTOR_32K 0x8000U
|
||||||
|
#define F_PAGE_256 0x100U
|
||||||
|
#define F_SECTOR_4K 0x1000U
|
||||||
|
#define F_FLASH_SIZE_BYTES 0x4000000U
|
||||||
|
#define F_SECTOR_ERASE_SZ F_SECTOR_128K
|
||||||
|
#ifdef CONFIG_FSPI_4K_ERASE
|
||||||
|
#define F_SECTOR_ERASE_SZ F_SECTOR_4K
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef NXP_WARM_BOOT
|
||||||
|
#define FLASH_WR_COMP_WAIT_BY_NOP_COUNT 0x20000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif /* FLASH_INFO_H */
|
||||||
122
include/drivers/nxp/flexspi/fspi_api.h
Normal file
122
include/drivers/nxp/flexspi/fspi_api.h
Normal file
|
|
@ -0,0 +1,122 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2021 NXP
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @file fspi_api.h
|
||||||
|
* @brief This file contains the FlexSPI/FSPI API to communicate
|
||||||
|
* to attached Slave device.
|
||||||
|
* @addtogroup FSPI_API
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef FSPI_API_H
|
||||||
|
#define FSPI_API_H
|
||||||
|
|
||||||
|
#if DEBUG_FLEXSPI
|
||||||
|
#define SZ_57M 0x3900000u
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* Basic set of APIs.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @details AHB read/IP Read, decision to be internal to API
|
||||||
|
* Minimum Read size = 1Byte
|
||||||
|
* @param[in] src_off source offset from where data to read from flash
|
||||||
|
* @param[out] des Destination location where data needs to be copied
|
||||||
|
* @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
|
||||||
|
*
|
||||||
|
* @return XSPI_SUCCESS or error code
|
||||||
|
*/
|
||||||
|
int xspi_read(uint32_t src_off, uint32_t *des, uint32_t len);
|
||||||
|
/*!
|
||||||
|
* @details Sector erase, Minimum size
|
||||||
|
* 256KB(0x40000)/128KB(0x20000)/64K(0x10000)/4K(0x1000)
|
||||||
|
* depending upon flash, Calls xspi_wren() internally
|
||||||
|
* @param[out] erase_offset Destination erase location on flash which
|
||||||
|
* has to be erased, needs to be multiple of 0x40000/0x20000/0x10000
|
||||||
|
* @param[in] erase_len length in bytes in Hex like 0x100000 for 1MB, minimum
|
||||||
|
* erase size is 1 sector(0x40000/0x20000/0x10000)
|
||||||
|
*
|
||||||
|
* @return XSPI_SUCCESS or error code
|
||||||
|
*/
|
||||||
|
int xspi_sector_erase(uint32_t erase_offset, uint32_t erase_len);
|
||||||
|
/*!
|
||||||
|
* @details IP write, For writing data to flash, calls xspi_wren() internally.
|
||||||
|
* Single/multiple page write can start @any offset, but performance will be low
|
||||||
|
* due to ERRATA
|
||||||
|
* @param[out] dst_off Destination location on flash where data needs to
|
||||||
|
* be written
|
||||||
|
* @param[in] src source offset from where data to be read
|
||||||
|
* @param[in] len length in bytes,where 1-word=4-bytes/32-bits
|
||||||
|
*
|
||||||
|
* @return XSPI_SUCCESS or error code
|
||||||
|
*/
|
||||||
|
int xspi_write(uint32_t dst_off, void *src, uint32_t len);
|
||||||
|
/*!
|
||||||
|
* @details fspi_init, Init function.
|
||||||
|
* @param[in] uint32_t base_reg_addr
|
||||||
|
* @param[in] uint32_t flash_start_addr
|
||||||
|
*
|
||||||
|
* @return XSPI_SUCCESS or error code
|
||||||
|
*/
|
||||||
|
int fspi_init(uint32_t base_reg_addr, uint32_t flash_start_addr);
|
||||||
|
/*!
|
||||||
|
* @details is_flash_busy, Check if any erase or write or lock is
|
||||||
|
* pending on flash/slave
|
||||||
|
* @param[in] void
|
||||||
|
*
|
||||||
|
* @return TRUE/FLASE
|
||||||
|
*/
|
||||||
|
bool is_flash_busy(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* Advanced set of APIs.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @details Write enable, to be used by advance users only.
|
||||||
|
* Step 1 for sending write commands to flash.
|
||||||
|
* @param[in] dst_off destination offset where data will be written
|
||||||
|
*
|
||||||
|
* @return XSPI_SUCCESS or error code
|
||||||
|
*/
|
||||||
|
int xspi_wren(uint32_t dst_off);
|
||||||
|
/*!
|
||||||
|
* @details AHB read, meaning direct memory mapped access to flash,
|
||||||
|
* Minimum Read size = 1Byte
|
||||||
|
* @param[in] src_off source offset from where data to read from flash,
|
||||||
|
* needs to be word aligned
|
||||||
|
* @param[out] des Destination location where data needs to be copied
|
||||||
|
* @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
|
||||||
|
*
|
||||||
|
* @return XSPI_SUCCESS or error code
|
||||||
|
*/
|
||||||
|
int xspi_ahb_read(uint32_t src_off, uint32_t *des, uint32_t len);
|
||||||
|
/*!
|
||||||
|
* @details IP read, READ via RX buffer from flash, minimum READ size = 1Byte
|
||||||
|
* @param[in] src_off source offset from where data to be read from flash
|
||||||
|
* @param[out] des Destination location where data needs to be copied
|
||||||
|
* @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
|
||||||
|
*
|
||||||
|
* @return XSPI_SUCCESS or error code
|
||||||
|
*/
|
||||||
|
int xspi_ip_read(uint32_t src_off, uint32_t *des, uint32_t len);
|
||||||
|
/*!
|
||||||
|
* @details CHIP erase, Erase complete chip in one go
|
||||||
|
*
|
||||||
|
* @return XSPI_SUCCESS or error code
|
||||||
|
*/
|
||||||
|
int xspi_bulk_erase(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* Add test cases to confirm flash read/erase/write functionality.
|
||||||
|
*/
|
||||||
|
void fspi_test(uint32_t fspi_test_addr, uint32_t size, int extra);
|
||||||
|
#endif /* FSPI_API_H */
|
||||||
28
include/drivers/nxp/flexspi/xspi_error_codes.h
Normal file
28
include/drivers/nxp/flexspi/xspi_error_codes.h
Normal file
|
|
@ -0,0 +1,28 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2020 NXP
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* error codes */
|
||||||
|
#ifndef XSPI_ERROR_CODES_H
|
||||||
|
#define XSPI_ERROR_CODES_H
|
||||||
|
|
||||||
|
#include <errno.h>
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
XSPI_SUCCESS = 0,
|
||||||
|
XSPI_READ_FAIL = ELAST + 1,
|
||||||
|
XSPI_ERASE_FAIL,
|
||||||
|
XSPI_IP_READ_FAIL,
|
||||||
|
XSPI_AHB_READ_FAIL,
|
||||||
|
XSPI_IP_WRITE_FAIL,
|
||||||
|
XSPI_AHB_WRITE_FAIL,
|
||||||
|
XSPI_BLOCK_TIMEOUT,
|
||||||
|
XSPI_UNALIGN_ADDR,
|
||||||
|
XSPI_UNALIGN_SIZE,
|
||||||
|
} XSPI_STATUS_CODES;
|
||||||
|
#undef ELAST
|
||||||
|
#define ELAST XSPI_STATUS_CODES.XSPI_UNALIGN_SIZE
|
||||||
|
#endif
|
||||||
Loading…
Add table
Reference in a new issue