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nxp: adding gic apis for nxp soc
GIC api used by NXP SoC is based on: - arm provided drivers: /drivers/arm/gic Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: If3d470256e5bd078614f191e56062c4fbd97f8bd
This commit is contained in:
Pankaj Gupta
parent
e3e48b5c38
commit
b53334dac4
5 changed files with 386 additions and 0 deletions
46
drivers/nxp/gic/gic.mk
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46
drivers/nxp/gic/gic.mk
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# Copyright 2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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#------------------------------------------------------------------------------
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#
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# Select the GIC files
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#
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# -----------------------------------------------------------------------------
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ifeq (${ADD_GIC},)
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ADD_GIC := 1
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ifeq ($(GIC), GIC400)
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include drivers/arm/gic/v2/gicv2.mk
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GIC_SOURCES += ${GICV2_SOURCES}
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GIC_SOURCES += ${PLAT_DRIVERS_PATH}/gic/ls_gicv2.c \
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plat/common/plat_gicv2.c
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PLAT_INCLUDES += -I${PLAT_DRIVERS_PATH}/gic/include/gicv2
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else
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ifeq ($(GIC), GIC500)
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include drivers/arm/gic/v3/gicv3.mk
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GIC_SOURCES += ${GICV3_SOURCES}
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GIC_SOURCES += ${PLAT_DRIVERS_PATH}/gic/ls_gicv3.c \
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plat/common/plat_gicv3.c
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PLAT_INCLUDES += -I${PLAT_DRIVERS_PATH}/gic/include/gicv3
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else
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$(error -> GIC type not set!)
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endif
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endif
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ifeq (${BL_COMM_GIC_NEEDED},yes)
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BL_COMMON_SOURCES += ${GIC_SOURCES}
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else
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ifeq (${BL2_GIC_NEEDED},yes)
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BL2_SOURCES += ${GIC_SOURCES}
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endif
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ifeq (${BL31_GIC_NEEDED},yes)
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BL31_SOURCES += ${GIC_SOURCES}
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endif
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endif
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endif
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# -----------------------------------------------------------------------------
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72
drivers/nxp/gic/include/gicv2/plat_gic.h
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72
drivers/nxp/gic/include/gicv2/plat_gic.h
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_GICV2_H
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#define PLAT_GICV2_H
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#include <drivers/arm/gicv2.h>
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/* register offsets */
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#define GICD_CTLR_OFFSET 0x0
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#define GICD_CPENDSGIR3_OFFSET 0xF1C
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#define GICD_SPENDSGIR3_OFFSET 0xF2C
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#define GICD_SGIR_OFFSET 0xF00
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#define GICD_IGROUPR0_OFFSET 0x080
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#define GICD_TYPER_OFFSET 0x0004
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#define GICD_ISENABLER0_OFFSET 0x0100
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#define GICD_ICENABLER0_OFFSET 0x0180
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#define GICD_IPRIORITYR3_OFFSET 0x040C
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#define GICD_ISENABLERn_OFFSET 0x0100
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#define GICD_ISACTIVER0_OFFSET 0x300
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#define GICC_CTLR_OFFSET 0x0
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#define GICC_PMR_OFFSET 0x0004
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#define GICC_IAR_OFFSET 0x000C
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#define GICC_DIR_OFFSET 0x1000
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#define GICC_EOIR_OFFSET 0x0010
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/* bitfield masks */
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#define GICC_CTLR_EN_GRP0 0x1
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#define GICC_CTLR_EN_GRP1 0x2
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#define GICC_CTLR_EOImodeS_MASK 0x200
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#define GICC_CTLR_DIS_BYPASS 0x60
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#define GICC_CTLR_CBPR_MASK 0x10
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#define GICC_CTLR_FIQ_EN_MASK 0x8
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#define GICC_CTLR_ACKCTL_MASK 0x4
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#define GICC_PMR_FILTER 0xFF
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#define GICD_CTLR_EN_GRP0 0x1
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#define GICD_CTLR_EN_GRP1 0x2
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#define GICD_IGROUP0_SGI15 0x8000
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#define GICD_ISENABLE0_SGI15 0x8000
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#define GICD_ICENABLE0_SGI15 0x8000
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#define GICD_ISACTIVER0_SGI15 0x8000
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#define GICD_CPENDSGIR_CLR_MASK 0xFF000000
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#define GICD_IPRIORITY_SGI15_MASK 0xFF000000
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#define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000
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#define GICD_SPENDSGIR3_SGI15_OFFSET 0x18
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#ifndef __ASSEMBLER__
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/* GIC common API's */
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void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
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const uintptr_t nxp_gicc_addr,
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uint8_t plat_core_count,
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interrupt_prop_t *ls_interrupt_props,
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uint8_t ls_interrupt_prop_count,
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uint32_t *target_mask_array);
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void plat_ls_gic_init(void);
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void plat_ls_gic_cpuif_enable(void);
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void plat_ls_gic_cpuif_disable(void);
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void plat_ls_gic_redistif_on(void);
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void plat_ls_gic_redistif_off(void);
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void plat_gic_pcpu_init(void);
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/* GIC utility functions */
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void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
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#endif
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#endif /* PLAT_GICV2_H */
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114
drivers/nxp/gic/include/gicv3/plat_gic.h
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114
drivers/nxp/gic/include/gicv3/plat_gic.h
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@ -0,0 +1,114 @@
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_GICV3_H
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#define PLAT_GICV3_H
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#include <drivers/arm/gicv3.h>
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/* offset between redistributors */
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#define GIC_RD_OFFSET 0x00020000
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/* offset between SGI's */
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#define GIC_SGI_OFFSET 0x00020000
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/* offset from rd base to sgi base */
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#define GIC_RD_2_SGI_OFFSET 0x00010000
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/* register offsets */
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#define GICD_CTLR_OFFSET 0x0
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#define GICD_CLR_SPI_SR 0x58
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#define GICD_IGROUPR_2 0x88
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#define GICD_ISENABLER_2 0x108
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#define GICD_ICENABLER_2 0x188
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#define GICD_ICPENDR_2 0x288
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#define GICD_ICACTIVER_2 0x388
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#define GICD_IPRIORITYR_22 0x458
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#define GICD_ICFGR_5 0xC14
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#define GICD_IGRPMODR_2 0xD08
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#define GICD_IROUTER60_OFFSET 0x61e0
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#define GICD_IROUTER76_OFFSET 0x6260
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#define GICD_IROUTER89_OFFSET 0x62C8
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#define GICD_IROUTER112_OFFSET 0x6380
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#define GICD_IROUTER113_OFFSET 0x6388
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#define GICR_ICENABLER0_OFFSET 0x180
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#define GICR_CTLR_OFFSET 0x0
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#define GICR_IGROUPR0_OFFSET 0x80
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#define GICR_IGRPMODR0_OFFSET 0xD00
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#define GICR_IPRIORITYR3_OFFSET 0x40C
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#define GICR_ICPENDR0_OFFSET 0x280
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#define GICR_ISENABLER0_OFFSET 0x100
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#define GICR_TYPER_OFFSET 0x8
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#define GICR_WAKER_OFFSET 0x14
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#define GICR_ICACTIVER0_OFFSET 0x380
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#define GICR_ICFGR0_OFFSET 0xC00
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/* bitfield masks */
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#define GICD_CTLR_EN_GRP_MASK 0x7
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#define GICD_CTLR_EN_GRP_1NS 0x2
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#define GICD_CTLR_EN_GRP_1S 0x4
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#define GICD_CTLR_EN_GRP_0 0x1
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#define GICD_CTLR_ARE_S_MASK 0x10
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#define GICD_CTLR_RWP 0x80000000
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#define GICR_ICENABLER0_SGI15 0x00008000
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#define GICR_CTLR_RWP 0x8
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#define GICR_CTLR_DPG0_MASK 0x2000000
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#define GICR_IGROUPR0_SGI15 0x00008000
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#define GICR_IGRPMODR0_SGI15 0x00008000
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#define GICR_ISENABLER0_SGI15 0x00008000
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#define GICR_IPRIORITYR3_SGI15_MASK 0xFF000000
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#define GICR_ICPENDR0_SGI15 0x8000
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#define GIC_SPI_89_MASK 0x02000000
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#define GIC_SPI89_PRIORITY_MASK 0xFF00
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#define GIC_IRM_SPI89 0x80000000
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#define GICD_IROUTER_VALUE 0x100
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#define GICR_WAKER_SLEEP_BIT 0x2
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#define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1)
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#define ICC_SRE_EL3_SRE 0x1
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#define ICC_IGRPEN0_EL1_EN 0x1
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#define ICC_CTLR_EL3_CBPR_EL1S 0x1
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#define ICC_CTLR_EL3_RM 0x20
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#define ICC_CTLR_EL3_EOIMODE_EL3 0x4
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#define ICC_CTLR_EL3_PMHE 0x40
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#define ICC_PMR_EL1_P_FILTER 0xFF
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#define ICC_IAR0_EL1_SGI15 0xF
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#define ICC_SGI0R_EL1_INTID 0x0F000000
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#define ICC_IAR0_INTID_SPI_89 0x59
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#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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#define ICC_SRE_EL3 S3_6_C12_C12_5
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_SRE_EL2 S3_4_C12_C9_5
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#define ICC_CTLR_EL1 S3_0_C12_C12_4
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#ifndef __ASSEMBLER__
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/* GIC common API's */
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typedef unsigned int (*my_core_pos_fn)(void);
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void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
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const uintptr_t nxp_gicr_addr,
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uint8_t plat_core_count,
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interrupt_prop_t *ls_interrupt_props,
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uint8_t ls_interrupt_prop_count,
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uintptr_t *target_mask_array,
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mpidr_hash_fn mpidr_to_core_pos);
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//void plat_ls_gic_driver_init(void);
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void plat_ls_gic_init(void);
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void plat_ls_gic_cpuif_enable(void);
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void plat_ls_gic_cpuif_disable(void);
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void plat_ls_gic_redistif_on(void);
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void plat_ls_gic_redistif_off(void);
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void plat_gic_pcpu_init(void);
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#endif
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#endif /* PLAT_GICV3_H */
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76
drivers/nxp/gic/ls_gicv2.c
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76
drivers/nxp/gic/ls_gicv2.c
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <gicv2.h>
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#include <plat_gic.h>
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/*
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* NXP common helper to initialize the GICv3 only driver.
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*/
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void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr,
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uintptr_t nxp_gicc_addr,
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uint8_t plat_core_count,
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interrupt_prop_t *ls_interrupt_props,
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uint8_t ls_interrupt_prop_count,
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uint32_t *target_mask_array)
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{
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static struct gicv2_driver_data ls_gic_data;
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ls_gic_data.gicd_base = nxp_gicd_addr;
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ls_gic_data.gicc_base = nxp_gicc_addr;
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ls_gic_data.target_masks = target_mask_array;
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ls_gic_data.target_masks_num = plat_core_count;
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ls_gic_data.interrupt_props = ls_interrupt_props;
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ls_gic_data.interrupt_props_num = ls_interrupt_prop_count;
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gicv2_driver_init(&ls_gic_data);
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}
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void plat_ls_gic_init(void)
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{
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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/******************************************************************************
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* ARM common helper to enable the GICv2 CPU interface
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*****************************************************************************/
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void plat_ls_gic_cpuif_enable(void)
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{
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gicv2_cpuif_enable();
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}
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/******************************************************************************
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* ARM common helper to disable the GICv2 CPU interface
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*****************************************************************************/
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void plat_ls_gic_cpuif_disable(void)
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{
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gicv2_cpuif_disable();
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}
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/******************************************************************************
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* NXP common helper to initialize GICv2 per cpu
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*****************************************************************************/
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void plat_gic_pcpu_init(void)
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{
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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/******************************************************************************
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* Stubs for Redistributor power management. Although GICv2 doesn't have
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* Redistributor interface, these are provided for the sake of uniform GIC API
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*****************************************************************************/
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void plat_ls_gic_redistif_on(void)
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{
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}
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void plat_ls_gic_redistif_off(void)
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{
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}
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78
drivers/nxp/gic/ls_gicv3.c
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78
drivers/nxp/gic/ls_gicv3.c
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <drivers/arm/gicv3.h>
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#include <plat_gic.h>
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#include <plat/common/platform.h>
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/*
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* NXP common helper to initialize the GICv3 only driver.
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*/
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void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr,
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uintptr_t nxp_gicr_addr,
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uint8_t plat_core_count,
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interrupt_prop_t *ls_interrupt_props,
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uint8_t ls_interrupt_prop_count,
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uintptr_t *target_mask_array,
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mpidr_hash_fn mpidr_to_core_pos)
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{
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static struct gicv3_driver_data ls_gic_data;
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ls_gic_data.gicd_base = nxp_gicd_addr;
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ls_gic_data.gicr_base = nxp_gicr_addr;
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ls_gic_data.interrupt_props = ls_interrupt_props;
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ls_gic_data.interrupt_props_num = ls_interrupt_prop_count;
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ls_gic_data.rdistif_num = plat_core_count;
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ls_gic_data.rdistif_base_addrs = target_mask_array;
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ls_gic_data.mpidr_to_core_pos = mpidr_to_core_pos;
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gicv3_driver_init(&ls_gic_data);
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}
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void plat_ls_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/*
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* NXP common helper to enable the GICv3 CPU interface
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*/
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void plat_ls_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/*
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* NXP common helper to disable the GICv3 CPU interface
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*/
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void plat_ls_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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/*
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* NXP common helper to initialize the per cpu distributor interface in GICv3
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*/
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void plat_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/*
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* Stubs for Redistributor power management. Although GICv3 doesn't have
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* Redistributor interface, these are provided for the sake of uniform GIC API
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*/
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void plat_ls_gic_redistif_on(void)
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{
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}
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void plat_ls_gic_redistif_off(void)
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{
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}
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