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Add v0.3 release documentation
Update the readme.md and change-log.md with release information. Also, remove the "Detailed changes since last release" section of the change-log.md since the same information can be found in the GIT commit messages. Fixes ARM-software/tf-issues#22. Change-Id: I968cc8aaf588aa5c34ba8f1c12a5b797a46e04f5
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ARM Trusted Firmware
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====================
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ARM Trusted Firmware - version 0.3
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==================================
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Detailed changes since last release
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-----------------------------------
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New features
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------------
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* Support for Foundation FVP Version 2.0 added.
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The documented UEFI configuration disables some devices that are unavailable
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in the Foundation FVP, including MMC and CLCD. The resultant UEFI binary can
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be used on the AEMv8 and Cortex-A57-A53 FVPs, as well as the Foundation FVP.
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be used on the AEMv8 and Cortex-A57-A53 Base FVPs, as well as the Foundation
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FVP.
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NOTE: The software will not work on Version 1.0 of the Foundation FVP.
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* Regression-checked against latest Base FVPs (Version 5.2).
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* Enabled third party contributions. Added a new contributing.md containing
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instructions for how to contribute and updated copyright text in all files
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to acknowledge contributors.
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* The supplied FDTs expose the Interrupt Translation Service (ITS) available
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in GICv3.
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* Fixed various GCC compiler warnings.
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* Unmask SError and Debug exceptions in the trusted firmware.
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Also route external abort and SError interrupts to EL3.
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* The amount of physical RAM available to Linux as specified in the FDTs for
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Base FVPs have been increased from 2GB to 4GB. This resolves the issue of
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failing to start user-space when using a RAM-disk file-system.
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* Build products are now created in a separate build directory tree.
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* Analyze at link-time whether bootloader images will fit in memory and won't
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overlap each other at run time. If it is not the case then image linking
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will now fail.
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* Reduce the size of the bootloader images by cutting some sections out of
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their disk images and allocating them at load time, whenever possible.
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* Properly initialise the C runtime environment. C code can now safely assume
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that global variables are initialised to 0 and that initialised data holds
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the correct value.
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* General changes on the memory layout: some sections have been moved, some of
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them have been merged together, and some alignment constraints on sections
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have changed.
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* Enable third party contributions. Add a new contributing.md containing
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instructions for how to contribute and update copyright text in all files to
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acknowledge contributors.
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* The wake up enable bit in the FVP power controller is cleared when a cpu is
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physically powered up to prevent a spurious wake up from a subsequent cpu
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off state.
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* Definitions of some constants related to the PSCI api calls AFFINITY_INFO
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and CPU_SUSPEND have been corrected.
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* A bug which triggered an error condition in the code executed after a cpu
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is powered on, if a non zero context id parameter was passed in the PSCI
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CPU_ON and CPU_SUSPEND api calls has been corrected.
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* A restriction in the FVP code which did not allow the non-secure entrypoint
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to lie outside the DRAM has been removed.
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* The PSCI CPU_SUSPEND api has been stabilised to an extent where it can be
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* The PSCI CPU_SUSPEND API has been stabilised to the extent where it can be
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used for entry into power down states with the following restrictions:
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- Entry into standby states is not supported.
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- The api is only supported on the AEMv8 Base FVP.
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- The API is only supported on the AEMv8 and Cortex-A57-A53 Base FVPs.
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* The PSCI AFFINITY_INFO api has undergone limited testing on the AEMv8 Base
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FVP to allow experimental use.
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* Locks corresponding to each affinity level are acquired and released in
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the correct sequence in the PSCI implementation. Invocation of the PSCI
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CPU_SUSPEND and CPU_OFF apis simultaneously across cpus & clusters should
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not result in unexpected behaviour.
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* The API to return the memory layout structures for each bootloader stage has
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undergone change. A pointer to these structures is returned instead of their
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copy.
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* The PSCI AFFINITY_INFO api has undergone limited testing on the Base FVPs to
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allow experimental use.
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* Required C library and runtime header files are now included locally in ARM
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Trusted Firmware instead of depending on the toolchain standard include
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paths. The local implementation has been cleaned up and reduced in scope.
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Implementations for `putchar()` and `strchr()` were added to the local C
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library.
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* GCC compiler built-in function support has been disabled in order to improve
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compiler independence.
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* Added I/O abstraction framework, primarily to allow generic code to load
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images in a platform-independent way. The existing image loading code has
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been reworked to use the new framework. Semi-hosting and NOR flash I/O
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drivers are provided.
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* The references to GitHub issues in the documentation now to point to a
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separate issue tracking repository
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https://github.com/ARM-software/tf-issues.
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* Introduced Firmware Image Package (FIP) handling code and tools. A FIP
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combines multiple firmware images with a Table of Contents (ToC) into a
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single binary image. The new FIP driver is another type of I/O driver. The
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Makefile builds a FIP by default and the FVP platform code expect to load a
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FIP from NOR flash, although some support for image loading using semi-
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hosting is retained.
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* Cleared bits in the architectural trap feature register (CPTR_EL3) during
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early boot to prevent traps when accessing certain registers, including
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floating point registers. Also added `-mgeneral-regs-only` flag to GCC
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settings to prevent generation of code using floating point registers.
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NOTE: Building a FIP by default is a non-backwards-compatible change.
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* The GICv3 distributor can have more ports than CPUs are available in the
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system. The GICv3 re-distributors are probed to work out which
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re-distributor should be used with which CPU.
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NOTE: Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into
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DRAM instead of expecting this to be pre-loaded at known location. This is
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also a non-backwards-compatible change.
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* Add multi-platform support to the build system. The user may now specify
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which platform to build using PLAT=<platform> as part of the make command
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line. Default behaviour is to make all platforms. New platforms are
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automatically detected by the make file when they are added to the plat
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directory.
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NOTE: Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that
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it knows the new location to execute from and no longer needs to copy
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particular code modules to DRAM itself.
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* An issue in the PSCI implementation has been fixed which could result in the
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power down of an affinity instance at level X even though at least one
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affinity instance at level X - 1 does not allow this.
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* Reworked BL2 to BL3-1 handover interface. A new composite structure
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(bl31_args) holds the superset of information that needs to be passed from
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BL2 to BL3-1, including information on how handover execution control to
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BL3-2 (if present) and BL3-3 (non-trusted firmware).
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* Added library support for CPU context management, allowing the saving and
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restoring of
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- Shared system registers between Secure-EL1 and EL1.
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- VFP registers.
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- Essential EL3 system registers.
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* Added a framework for implementing EL3 runtime services. Reworked the PSCI
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implementation to be one such runtime service.
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* Reworked the exception handling logic, making use of both SP_EL0 and SP_EL3
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stack pointers for determining the type of exception, managing general
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purpose and system register context on exception entry/exit, and handling
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SMCs. SMCs are directed to the correct EL3 runtime service.
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* Added support for a Test Secure-EL1 Payload (TSP) and a corresponding
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Dispatcher (TSPD), which is loaded as an EL3 runtime service. The TSPD
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implements Secure Monitor functionality such as world switching and
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EL1 context management, and is responsible for communication with the TSP.
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NOTE: The TSPD does not yet contain support for secure world interrupts.
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NOTE: The TSP/TSPD is not built by default.
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Issues resolved since last release
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----------------------------------
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* Support has been added for switching context between secure and normal
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worlds in EL3.
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* PSCI API calls `AFFINITY_INFO` & `PSCI_VERSION` have now been tested (to
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a limited extent).
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* The ARM Trusted Firmware build artifacts are now placed in the `./build`
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directory and sub-directories instead of being placed in the root of the
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project.
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* The ARM Trusted Firmware is now free from build warnings. Build warnings
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are now treated as errors.
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* The ARM Trusted Firmware now provides C library support locally within the
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project to maintain compatibility between toolchains/systems.
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* The PSCI locking code has been reworked so it no longer takes locks in an
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incorrect sequence.
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* The RAM-disk method of loading a Linux file-system has been confirmed to
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work with the ARM Trusted Firmware and Linux kernel version (based on
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version 3.13) used in this release, for both Foundation and Base FVPs.
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Known issues
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------------
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The following is a list of issues which are expected to be fixed in the future
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releases of the ARM Trusted Firmware.
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* The TrustZone Address Space Controller (TZC-400) is not being programmed
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yet. Use of model parameter `-C bp.secure_memory=1` is not supported.
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* No support yet for secure world interrupt handling.
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* GICv3 support is experimental. The Linux kernel patches to support this are
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not widely available. There are known issues with GICv3 initialization in
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the ARM Trusted Firmware.
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* Dynamic image loading is not available yet. The current image loader
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implementation (used to load BL2 and all subsequent images) has some
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limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead
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to loading errors, even if the images should theoretically fit in memory.
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* The ARM Trusted Firmware uses too much on-chip Trusted SRAM. Currently the
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Test Secure-EL1 Payload (BL3-2) executes in Trusted DRAM since there is not
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enough SRAM. A number of RAM usage enhancements have been identified to
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rectify this situation.
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* CPU idle does not work on the advertised version of the Foundation FVP.
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Some FVP fixes are required that are not available externally at the time
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of writing.
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* Various bugs in ARM Trusted Firmware, UEFI and the Linux kernel have been
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observed when using Linaro toolchain versions later than 13.11. Although
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most of these have been fixed, some remain at the time of writing. These
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mainly seem to relate to a subtle change in the way the compiler converts
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between 64-bit and 32-bit values (e.g. during casting operations), which
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reveals previously hidden bugs in client code.
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* The tested filesystem used for this release (Linaro AArch64 OpenEmbedded
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14.01) does not report progress correctly in the console. It only seems to
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produce error output, not standard output. It otherwise appears to function
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correctly. Other filesystem versions on the same software stack do not
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exhibit the problem.
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* The Makefile structure doesn't make it easy to separate out parts of the
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Trusted Firmware for re-use in platform ports, for example if only BL3-1 is
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required in a platform port. Also, dependency checking in the Makefile is
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flawed.
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* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
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its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
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ARM Trusted Firmware - version 0.2
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@ -177,11 +223,6 @@ releases of the ARM Trusted Firmware.
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to the kernel.
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Detailed changes since last release
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-----------------------------------
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First source release - not applicable.
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- - - - - - - - - - - - - - - - - - - - - - - - - -
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_Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
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64
readme.md
64
readme.md
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ARM Trusted Firmware - version 0.2
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ARM Trusted Firmware - version 0.3
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==================================
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ARM Trusted Firmware provides a reference implementation of secure world
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software for [ARMv8-A], including Exception Level 3 (EL3) software. This first
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software for [ARMv8-A], including Exception Level 3 (EL3) software. This
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release focuses on support for ARM's [Fixed Virtual Platforms (FVPs)] [FVP].
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The intent is to provide a reference implementation of various ARM interface
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@ -11,9 +11,9 @@ Board Boot Requirements (TBBR) and [Secure Monitor] [TEE-SMC] code. As far as
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possible the code is designed for reuse or porting to other ARMv8-A model and
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hardware platforms.
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This release is the first one as source code: an initial prototype
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release was available in binary form in the [Linaro AArch64 OpenEmbedded
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Engineering Build] [AArch64 LEB] to support the new FVP Base platform
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This release builds on the previous source code release, which has been
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available in source and binary form since the [Linaro AArch64 OpenEmbedded 13.11
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Engineering Build] [AArch64 LEB]. These support the Base FVP platform
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models from ARM.
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ARM will continue development in collaboration with interested parties to
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@ -32,14 +32,16 @@ source files.
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This Release
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------------
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This software is an early implementation of the Trusted Firmware. Only
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This release is an incomplete implementation of the Trusted Firmware. Only
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limited functionality is provided at present and it has not been optimized or
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subjected to extended robustness or stress testing.
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### Functionality
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* Initial implementation of a subset of the Trusted Board Boot Requirements
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Platform Design Document (PDD).
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Platform Design Document (PDD). This includes packaging the various firmware
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images into a Firmware Image Package (FIP) to be loaded from non-volatile
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storage.
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* Initializes the secure world (for example, exception vectors, control
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registers, GIC and interrupts for the platform), before transitioning into
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@ -52,10 +54,16 @@ subjected to extended robustness or stress testing.
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if available, otherwise EL1.
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* Handles SMCs (Secure Monitor Calls) conforming to the [SMC Calling
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Convention PDD] [SMCCC].
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Convention PDD] [SMCCC] using an EL3 runtime services framework.
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* Handles SMCs relating to the [Power State Coordination Interface PDD] [PSCI]
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for the Secondary CPU Boot and CPU hotplug use-cases.
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for the Secondary CPU Boot, CPU hotplug and CPU idle use-cases.
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* A Test Secure-EL1 Payload and Dispatcher to demonstrate Secure Monitor
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functionality such as world switching and EL1 context management. This
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also demonstrates Secure-EL1 interaction with PSCI. Some of this
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functionality is provided in library form for re-use by other Secure-EL1
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Payload Dispatchers.
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For a full list of updated functionality and implementation details, please
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see the [User Guide]. The [Change Log] provides details of changes made
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This release of the Trusted Firmware has been tested on the following ARM
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[FVP]s (64-bit versions only):
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* `FVP_Base_AEMv8A-AEMv8A` (Version 5.1, Build 0.8.5108).
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* `FVP_Base_Cortex-A57x4-A53x4` (Version 5.1, Build 0.8.5108).
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* `FVP_Base_Cortex-A57x1-A53x1` (Version 5.1, Build 0.8.5108).
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* `Foundation_v8` (Version 2.0, Build 0.8.5206)
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* `FVP_Base_AEMv8A-AEMv8A` (Version 5.4, Build 0.8.5405)
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* `FVP_Base_Cortex-A57x4-A53x4` (Version 5.4, Build 0.8.5405)
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* `FVP_Base_Cortex-A57x1-A53x1` (Version 5.4, Build 0.8.5405)
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These models can be licensed from ARM: see [www.arm.com/fvp] [FVP].
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For an updated list of supported platforms, please see the [Change Log].
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The Foundation FVP can be downloaded free of charge. The Base FVPs can be
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licensed from ARM: see [www.arm.com/fvp] [FVP].
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### Still to Come
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* Complete implementation of the [PSCI] specification.
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* Secure memory, Secure monitor, Test Secure OS & Secure interrupts.
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* Secure memory, Secure interrupts and support for other types of Secure-EL1
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Payloads.
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* Booting the firmware from a block device.
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* Booting the firmware from a Virtio block device.
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* Completing the currently experimental GICv3 support.
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For a full list of detailed issues in the current code, please see the [Change
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Log].
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Log] and the [GitHub issue tracker].
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Getting Started
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See the [User Guide] for instructions on how to install, build and use
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the Trusted Firmware with the ARM [FVP]s.
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See the [Firmware Design] for information on how the ARM Trusted Firmware works.
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See the [Porting Guide] as well for information about how to use this
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software on another ARMv8-A platform.
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@ -107,8 +118,7 @@ project.
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### Feedback and support
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ARM welcomes any feedback on the Trusted Firmware. Please send feedback using
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the [GitHub issue tracker](
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https://github.com/ARM-software/tf-issues/issues).
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the [GitHub issue tracker].
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ARM licensees may contact ARM directly via their partner managers.
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@ -123,11 +133,13 @@ _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._
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[Acknowledgements]: ./acknowledgements.md "Contributor acknowledgements"
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[Change Log]: ./docs/change-log.md
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[User Guide]: ./docs/user-guide.md
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[Firmware Design]: ./docs/firmware-design.md
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[Porting Guide]: ./docs/porting-guide.md
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[ARMv8-A]: http://www.arm.com/products/processors/armv8-architecture.php "ARMv8-A Architecture"
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[FVP]: http://www.arm.com/fvp "ARM's Fixed Virtual Platforms"
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[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022b/index.html "Power State Coordination Interface PDD (ARM DEN 0022B.b)"
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[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)"
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[TEE-SMC]: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php "Secure Monitor and TEEs"
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[AArch64 LEB]: http://releases.linaro.org/13.09/openembedded/aarch64 "Linaro AArch64 OpenEmbedded ARM Fast Model 13.09 Release"
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[ARMv8-A]: http://www.arm.com/products/processors/armv8-architecture.php "ARMv8-A Architecture"
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[FVP]: http://www.arm.com/fvp "ARM's Fixed Virtual Platforms"
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[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022b/index.html "Power State Coordination Interface PDD (ARM DEN 0022B.b)"
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[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)"
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[TEE-SMC]: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php "Secure Monitor and TEEs"
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[AArch64 LEB]: http://releases.linaro.org/13.11/openembedded/aarch64 "Linaro AArch64 OpenEmbedded ARM Fast Model 13.11 Release"
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[GitHub issue tracker]: https://github.com/ARM-software/tf-issues/issues
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