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Consolidate design and porting documentation
Consolidate firmware-design.md and porting-guide.pm so that recently added sections fit better with pre-existing sections. Make the documentation more consistent in use of terminology. Change-Id: Id87050b096122fbd845189dc2fe1cd17c3003468
This commit is contained in:
Dan Handley
parent
5e1e920075
commit
57de6d7274
2 changed files with 49 additions and 54 deletions
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@ -44,12 +44,13 @@ secondary CPUs are kept in a safe platform-specific state until the primary
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CPU has performed enough initialization to boot them.
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The cold boot path in this implementation of the ARM Trusted Firmware is divided
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into three stages (in order of execution):
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into five steps (in order of execution):
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* Boot Loader stage 1 (BL1)
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* Boot Loader stage 2 (BL2)
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* Boot Loader stage 3 (BL3-1). The '1' distinguishes this from other 3rd level
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boot loader stages.
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* Boot Loader stage 1 (BL1) _AP Trusted ROM_
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* Boot Loader stage 2 (BL2) _Trusted Boot Firmware_
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* Boot Loader stage 3-1 (BL3-1) _EL3 Runtime Firmware_
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* Boot Loader stage 3-2 (BL3-2) _Secure-EL1 Payload_ (optional)
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* Boot Loader stage 3-3 (BL3-3) _Non-trusted Firmware_
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The ARM Fixed Virtual Platforms (FVPs) provide trusted ROM, trusted SRAM and
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trusted DRAM regions. Each boot loader stage uses one or more of these
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@ -171,9 +172,9 @@ BL1 execution continues as follows:
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1. BL1 determines the amount of free trusted SRAM memory available by
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calculating the extent of its own data section, which also resides in
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trusted SRAM. BL1 loads a BL2 raw binary image from platform storage, at a
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platform-specific base address. The filename of the BL2 raw binary image
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must be `bl2.bin`. If the BL2 image file is not present or if there is not
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enough free trusted SRAM the following error message is printed:
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platform-specific base address. If the BL2 image file is not present or if
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there is not enough free trusted SRAM the following error message is
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printed:
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"Failed to load boot loader stage 2 (BL2) firmware."
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@ -198,7 +199,7 @@ BL1 execution continues as follows:
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### BL2
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BL1 loads and passes control to BL2 at Secure EL1. BL2 is linked against and
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BL1 loads and passes control to BL2 at Secure-EL1. BL2 is linked against and
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loaded at a platform-specific base address (more information can be found later
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in this document). The functionality implemented by BL2 is as follows.
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@ -217,60 +218,55 @@ BL2 does not perform any platform initialization that affects subsequent
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stages of the ARM Trusted Firmware or normal world software. It copies the
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information regarding the trusted SRAM populated by BL1 using a
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platform-specific mechanism. It calculates the limits of DRAM (main memory)
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to determine whether there is enough space to load the normal world software
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images. A platform defined base address is used to specify the load address for
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the BL3-1 image. It also defines the extents of memory available for use by the
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BL3-2 image.
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to determine whether there is enough space to load the BL3-3 image. A platform
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defined base address is used to specify the load address for the BL3-1 image.
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It also defines the extents of memory available for use by the BL3-2 image.
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#### Normal world image load
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#### BL3-1 (EL3 Runtime Firmware) image load
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BL2 loads the normal world firmware image (e.g. UEFI). BL2 relies on BL3-1 to
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pass control to the normal world software image it loads. Hence, BL2 populates
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a platform-specific area of memory with the entrypoint and Current Program
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Status Register (`CPSR`) of the normal world software image. The entrypoint is
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the load address of the normal world software image. The `CPSR` is determined as
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specified in Section 5.13 of the [PSCI PDD] [PSCI]. This information is passed
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to BL3-1.
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BL2 loads the BL3-1 image from platform storage into a platform-specific address
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in trusted SRAM. If there is not enough memory to load the image or image is
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missing it leads to an assertion failure. If the BL3-1 image loads successfully,
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BL2 updates the amount of trusted SRAM used and available for use by BL3-1.
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This information is populated at a platform-specific memory address.
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#### BL3-2 (Secure Payload) image load
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#### BL3-2 (Secure-EL1 Payload) image load
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BL2 loads the optional BL3-2 image. The image executes in the secure world. BL2
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BL2 loads the optional BL3-2 image from platform storage into a platform-
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specific region of secure memory. The image executes in the secure world. BL2
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relies on BL3-1 to pass control to the BL3-2 image, if present. Hence, BL2
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populates a platform- specific area of memory with the entrypoint and Current
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Program Status Register (`CPSR`) of the BL3-2 image. The entrypoint is the load
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address of the BL3-2 image. The `CPSR` is initialized with Secure EL1 and Stack
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pointer set to SP_EL1 (EL1h) as the mode, exception bits disabled (DAIF bits)
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and AArch64 execution state. This information is passed to BL3-1.
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populates a platform-specific area of memory with the entrypoint/load-address
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of the BL3-2 image. The value of the Saved Processor Status Register (`SPSR`)
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for entry into BL3-2 is not determined by BL2, it is initialized by the
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Secure-EL1 Payload Dispatcher (see later) within BL3-1, which is responsible for
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managing interaction with BL3-2. This information is passed to BL3-1.
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##### UEFI firmware load
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#### BL3-3 (Non-trusted Firmware) image load
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BL2 loads the BL3-3 (UEFI) image into non-secure memory as defined by the
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platform (`0x88000000` for FVPs), and arranges for BL3-1 to pass control to that
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location. As mentioned earlier, BL2 populates platform-specific memory with the
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entrypoint and `CPSR` of the BL3-3 image.
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BL2 loads the BL3-3 image (e.g. UEFI or other test or boot software) from
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platform storage into non-secure memory as defined by the platform
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(`0x88000000` for FVPs).
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#### BL3-1 image load and execution
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BL2 relies on BL3-1 to pass control to BL3-3 once secure state initialization is
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complete. Hence, BL2 populates a platform-specific area of memory with the
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entrypoint and Saved Program Status Register (`SPSR`) of the normal world
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software image. The entrypoint is the load address of the BL3-3 image. The
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`SPSR` is determined as specified in Section 5.13 of the [PSCI PDD] [PSCI]. This
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information is passed to BL3-1.
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#### BL3-1 (EL3 Runtime Firmware) execution
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BL2 execution continues as follows:
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1. BL2 loads the BL3-1 image into a platform-specific address in trusted SRAM
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and the BL3-3 image into a platform specific address in non-secure DRAM.
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The images are identified by the files `bl31.bin` and `bl33.bin` in
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platform storage. If there is not enough memory to load the images or the
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images are missing it leads to an assertion failure. If the BL3-1 image
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loads successfully, BL1 updates the amount of trusted SRAM used and
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available for use by BL3-1. This information is populated at a
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platform-specific memory address.
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2. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
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1. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
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BL3-1 entrypoint. The exception is handled by the SMC exception handler
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installed by BL1.
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3. BL1 turns off the MMU and flushes the caches. It clears the
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2. BL1 turns off the MMU and flushes the caches. It clears the
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`SCTLR_EL3.M/I/C` bits, flushes the data cache to the point of coherency
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and invalidates the TLBs.
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4. BL1 passes control to BL3-1 at the specified entrypoint at EL3.
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3. BL1 passes control to BL3-1 at the specified entrypoint at EL3.
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### BL3-1
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@ -299,8 +295,8 @@ SMC handler routine.
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BL3-1 performs detailed platform initialization, which enables normal world
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software to function correctly. It also retrieves entrypoint information for
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the normal world software image loaded by BL2 from the platform defined
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memory address populated by BL2.
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the BL3-3 image loaded by BL2 from the platform defined memory address populated
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by BL2.
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* GICv2 initialization:
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@ -1000,17 +996,15 @@ The tool can be found in `tools/fip_create`.
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### Loading from a Firmware Image Package (FIP)
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The Firmware Image Package (FIP) driver can load images from a binary package on
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non-volatile platform storage. For the FVPs this currently NOR FLASH. For
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information on how to load a FIP into FVP NOR FLASH see the "Running the
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software" section.
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non-volatile platform storage. For the FVPs this is currently NOR FLASH.
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Bootloader images are loaded according to the platform policy as specified in
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`plat/<platform>/plat_io_storage.c`. For the FVPs this means the platform will
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attempt to load images from a Firmware Image Package located at the start of NOR
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FLASH0.
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Currently the FVPs policy only allows for loading of known images. The platform
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policy can be modified to add additional images.
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Currently the FVP's policy only allows loading of a known set of images. The
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platform policy can be modified to allow additional images.
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8. Code Structure
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@ -616,7 +616,8 @@ address of Secure DRAM (`0x06000000`).
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The ARM FVP port also populates the `bl32_meminfo` field in the `bl31_args`
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structure pointed to by `bl2_to_bl31_args` with the extents of memory available
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for use by the BL3-2 image. The memory is allocated in the Secure DRAM from the
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address defined by the constant `BL32_BASE`.
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address defined by the constant `BL32_BASE`. The ARM FVP port currently loads
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the BL3-2 image at the Secure DRAM address `0x6002000`.
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The non-secure memory extents used for loading BL3-3 are also initialized in
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this function. This information is accessible in the `bl33_meminfo` field in
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