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fix(versal-net): use arm common GIC handlers

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Currently SGI interrupts are not received in secondary cores because
of issue in  GIC configuration. In current Versal NET specific GIC
functions, redistributor configuration is not happening properly.
Because of that SGI interrupt from one processor to another processor
is not transferring. So, use common GIC handlers which will iterate
over all GIC redistributor frames and discovers per cpu redistributor
frame. Also, it initializes corresponding interface in GICv3.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I1433260b8520d6a315fdf5df86bd0688f92d211a
This commit is contained in:
Jay Buddhabhatti 2023-10-05 21:55:28 -07:00
parent 79953190bc
commit b225926181
6 changed files with 24 additions and 201 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
plat/xilinx/versal_net/aarch64/versal_net_helpers.S
View file

@ -12,6 +12,7 @@
#include <platform_def.h> #include <platform_def.h>
.globl plat_arm_calc_core_pos
.globl plat_secondary_cold_boot_setup .globl plat_secondary_cold_boot_setup
.globl plat_is_my_cpu_primary .globl plat_is_my_cpu_primary
.globl platform_mem_init .globl platform_mem_init
@ -58,6 +59,16 @@ func plat_my_core_pos
b plat_core_pos_by_mpidr b plat_core_pos_by_mpidr
endfunc plat_my_core_pos endfunc plat_my_core_pos
/* -----------------------------------------------------
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
* This function uses the plat_core_pos_by_mpidr()
* definition to get the index of the calling CPU.
* -----------------------------------------------------
*/
func plat_arm_calc_core_pos
b plat_core_pos_by_mpidr
endfunc plat_arm_calc_core_pos
/* --------------------------------------------------------------------- /* ---------------------------------------------------------------------
* We don't need to carry out any memory initialization on Versal NET * We don't need to carry out any memory initialization on Versal NET
* platform. The Secure RAM is accessible straight away. * platform. The Secure RAM is accessible straight away.

4
plat/xilinx/versal_net/bl31_versal_net_setup.c
View file

@ -216,8 +216,8 @@ void bl31_platform_setup(void)
prepare_dtb(); prepare_dtb();
/* Initialize the gic cpu and distributor interfaces */ /* Initialize the gic cpu and distributor interfaces */
plat_versal_net_gic_driver_init(); plat_arm_gic_driver_init();
plat_versal_net_gic_init(); plat_arm_gic_init();
} }
void bl31_plat_runtime_setup(void) void bl31_plat_runtime_setup(void)

4
plat/xilinx/versal_net/plat_psci.c
View file

@ -108,8 +108,8 @@ static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
{ {
plat_versal_net_gic_pcpu_init(); plat_arm_gic_pcpu_init();
plat_versal_net_gic_cpuif_enable(); plat_arm_gic_cpuif_enable();
} }
static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)

14
plat/xilinx/versal_net/plat_psci_pm.c
View file

@ -66,7 +66,7 @@ static void versal_net_pwr_domain_off(const psci_power_state_t *target_state)
} }
/* Prevent interrupts from spuriously waking up this cpu */ /* Prevent interrupts from spuriously waking up this cpu */
plat_versal_net_gic_cpuif_disable(); plat_arm_gic_cpuif_disable();
/* /*
* Send request to PMC to power down the appropriate APU CPU * Send request to PMC to power down the appropriate APU CPU
@ -114,10 +114,10 @@ static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state
__func__, i, target_state->pwr_domain_state[i]); __func__, i, target_state->pwr_domain_state[i]);
} }
plat_versal_net_gic_cpuif_disable(); plat_arm_gic_cpuif_disable();
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
plat_versal_net_gic_save(); plat_arm_gic_save();
} }
state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
@ -135,10 +135,10 @@ static void versal_net_pwr_domain_on_finish(const psci_power_state_t *target_sta
(void)target_state; (void)target_state;
/* Enable the gic cpu interface */ /* Enable the gic cpu interface */
plat_versal_net_gic_pcpu_init(); plat_arm_gic_pcpu_init();
/* Program the gic per-cpu distributor or re-distributor interface */ /* Program the gic per-cpu distributor or re-distributor interface */
plat_versal_net_gic_cpuif_enable(); plat_arm_gic_cpuif_enable();
} }
/** /**
@ -163,10 +163,10 @@ static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *targe
/* APU was turned off, so restore GIC context */ /* APU was turned off, so restore GIC context */
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
plat_versal_net_gic_resume(); plat_arm_gic_resume();
} }
plat_versal_net_gic_cpuif_enable(); plat_arm_gic_cpuif_enable();
} }
/** /**

3
plat/xilinx/versal_net/platform.mk
View file

@ -121,6 +121,7 @@ BL31_SOURCES += plat/xilinx/common/plat_fdt.c \
${PLAT_PATH}/bl31_versal_net_setup.c \ ${PLAT_PATH}/bl31_versal_net_setup.c \
common/fdt_fixup.c \ common/fdt_fixup.c \
common/fdt_wrappers.c \ common/fdt_wrappers.c \
plat/arm/common/arm_gicv3.c \
${LIBFDT_SRCS} \ ${LIBFDT_SRCS} \
${PLAT_PATH}/sip_svc_setup.c \ ${PLAT_PATH}/sip_svc_setup.c \
${PLAT_PATH}/versal_net_gicv3.c ${XLAT_TABLES_LIB_SRCS}

189
plat/xilinx/versal_net/versal_net_gicv3.c
View file

@ -1,189 +0,0 @@
/*
* Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <common/interrupt_props.h>
#include <drivers/arm/gicv3.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <plat_private.h>
#include <platform_def.h>
/******************************************************************************
* The following functions are defined as weak to allow a platform to override
* the way the GICv3 driver is initialised and used.
*****************************************************************************/
#pragma weak plat_versal_net_gic_driver_init
#pragma weak plat_versal_net_gic_init
#pragma weak plat_versal_net_gic_cpuif_enable
#pragma weak plat_versal_net_gic_cpuif_disable
#pragma weak plat_versal_net_gic_pcpu_init
#pragma weak plat_versal_net_gic_redistif_on
#pragma weak plat_versal_net_gic_redistif_off
/* The GICv3 driver only needs to be initialized in EL3 */
static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
static const interrupt_prop_t versal_net_interrupt_props[] = {
PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
};
/*
* We save and restore the GICv3 context on system suspend. Allocate the
* data in the designated EL3 Secure carve-out memory.
*/
static gicv3_redist_ctx_t rdist_ctx __section(".versal_net_el3_tzc_dram");
static gicv3_dist_ctx_t dist_ctx __section(".versal_net_el3_tzc_dram");
/*
* MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
* to core position.
*
* Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
* values read from GICR_TYPER don't have an MT field. To reuse the same
* translation used for CPUs, we insert MT bit read from the PE's MPIDR into
* that read from GICR_TYPER.
*
* Assumptions:
*
* - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
* - No CPUs implemented in the system use affinity level 3.
*/
static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr)
{
mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
return plat_core_pos_by_mpidr(mpidr);
}
static const gicv3_driver_data_t versal_net_gic_data __unused = {
.gicd_base = PLAT_ARM_GICD_BASE,
.gicr_base = PLAT_ARM_GICR_BASE,
.interrupt_props = versal_net_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = rdistif_base_addrs,
.mpidr_to_core_pos = versal_net_gicv3_mpidr_hash
};
void __init plat_versal_net_gic_driver_init(void)
{
/*
* The GICv3 driver is initialized in EL3 and does not need
* to be initialized again in SEL1. This is because the S-EL1
* can use GIC system registers to manage interrupts and does
* not need GIC interface base addresses to be configured.
*/
#if IMAGE_BL31
gicv3_driver_init(&versal_net_gic_data);
#endif
}
/******************************************************************************
* Versal NET common helper to initialize the GIC. Only invoked by BL31
*****************************************************************************/
void __init plat_versal_net_gic_init(void)
{
gicv3_distif_init();
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
}
/******************************************************************************
* Versal NET common helper to enable the GIC CPU interface
*****************************************************************************/
void plat_versal_net_gic_cpuif_enable(void)
{
gicv3_cpuif_enable(plat_my_core_pos());
}
/******************************************************************************
* Versal NET common helper to disable the GIC CPU interface
*****************************************************************************/
void plat_versal_net_gic_cpuif_disable(void)
{
gicv3_cpuif_disable(plat_my_core_pos());
}
/******************************************************************************
* Versal NET common helper to initialize the per-cpu redistributor interface in
* GICv3
*****************************************************************************/
void plat_versal_net_gic_pcpu_init(void)
{
gicv3_rdistif_init(plat_my_core_pos());
}
/******************************************************************************
* Versal NET common helpers to power GIC redistributor interface
*****************************************************************************/
void plat_versal_net_gic_redistif_on(void)
{
gicv3_rdistif_on(plat_my_core_pos());
}
void plat_versal_net_gic_redistif_off(void)
{
gicv3_rdistif_off(plat_my_core_pos());
}
/******************************************************************************
* Versal NET common helper to save & restore the GICv3 on resume from system
* suspend
*****************************************************************************/
void plat_versal_net_gic_save(void)
{
/*
* If an ITS is available, save its context before
* the Redistributor using:
* gicv3_its_save_disable(gits_base, &its_ctx[i])
* Additionnaly, an implementation-defined sequence may
* be required to save the whole ITS state.
*/
/*
* Save the GIC Redistributors and ITS contexts before the
* Distributor context. As we only handle SYSTEM SUSPEND API,
* we only need to save the context of the CPU that is issuing
* the SYSTEM SUSPEND call, i.e. the current CPU.
*/
gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
/* Save the GIC Distributor context */
gicv3_distif_save(&dist_ctx);
/*
* From here, all the components of the GIC can be safely powered down
* as long as there is an alternate way to handle wakeup interrupt
* sources.
*/
}
void plat_versal_net_gic_resume(void)
{
/* Restore the GIC Distributor context */
gicv3_distif_init_restore(&dist_ctx);
/*
* Restore the GIC Redistributor and ITS contexts after the
* Distributor context. As we only handle SYSTEM SUSPEND API,
* we only need to restore the context of the CPU that issued
* the SYSTEM SUSPEND call.
*/
gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
/*
* If an ITS is available, restore its context after
* the Redistributor using:
* gicv3_its_restore(gits_base, &its_ctx[i])
* An implementation-defined sequence may be required to
* restore the whole ITS state. The ITS must also be
* re-enabled after this sequence has been executed.
*/
}