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fix(security): add CVE-2024-7881 mitigation to Cortex-X3

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This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1
for Cortex-X3 CPU.

[1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I410517d175a80fc6f459fa6ce5c30c0a38db9eaf
This commit is contained in:
Arvind Ram Prakash 2024-09-06 12:30:19 -05:00
parent 037a15f5c7
commit b0521a164a
1 changed files with 12 additions and 1 deletions
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13
lib/cpus/aarch64/cortex_x3.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -111,6 +111,17 @@ workaround_reset_end cortex_x3, CVE(2022, 23960)
check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
/* ---------------------------------
* Sets BIT41 of CPUACTLR6_EL1 which
* disables L1 Data cache prefetcher
* ---------------------------------
*/
sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41)
workaround_reset_end cortex_x3, CVE(2024, 7881)
check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
cpu_reset_func_start cortex_x3
/* Disable speculative loads */
msr SSBS, xzr