From b0521a164a8d61c95968e728df9af52be1a48553 Mon Sep 17 00:00:00 2001 From: Arvind Ram Prakash Date: Fri, 6 Sep 2024 12:30:19 -0500 Subject: [PATCH] fix(security): add CVE-2024-7881 mitigation to Cortex-X3 This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1 for Cortex-X3 CPU. [1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881 Signed-off-by: Arvind Ram Prakash Change-Id: I410517d175a80fc6f459fa6ce5c30c0a38db9eaf --- lib/cpus/aarch64/cortex_x3.S | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index 6becf7b2e..cbdfe3b34 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -111,6 +111,17 @@ workaround_reset_end cortex_x3, CVE(2022, 23960) check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 + /* --------------------------------- + * Sets BIT41 of CPUACTLR6_EL1 which + * disables L1 Data cache prefetcher + * --------------------------------- + */ + sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) +workaround_reset_end cortex_x3, CVE(2024, 7881) + +check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 + cpu_reset_func_start cortex_x3 /* Disable speculative loads */ msr SSBS, xzr