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Merge "feat(intel): support SDM mailbox safe inject seu error for Linux" into integration

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This commit is contained in:
Manish Pandey 2023-12-18 18:39:10 +01:00 • committed by TrustedFirmware Code Review
commit afa1da7506
4 changed files with 107 additions and 83 deletions
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2
plat/intel/soc/common/include/socfpga_mailbox.h
View file

@ -68,6 +68,7 @@
/* SEU Commands */ /* SEU Commands */
#define MBOX_CMD_SEU_ERR_READ 0x3C #define MBOX_CMD_SEU_ERR_READ 0x3C
#define MBOX_CMD_SAFE_INJECT_SEU_ERR 0x41
/* RSU Commands */ /* RSU Commands */
#define MBOX_GET_SUBPARTITION_TABLE 0x5A #define MBOX_GET_SUBPARTITION_TABLE 0x5A
@ -249,5 +250,6 @@ int mailbox_hps_stage_notify(uint32_t execution_stage);
int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf); int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf); int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len); int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len);
#endif /* SOCFPGA_MBOX_H */ #endif /* SOCFPGA_MBOX_H */

3
plat/intel/soc/common/include/socfpga_sip_svc.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -141,6 +141,7 @@
/* SEU ERR */ /* SEU ERR */
#define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099 #define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099
#define INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR 0xC200009A
#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF

8
plat/intel/soc/common/soc/socfpga_mailbox.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved. * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -696,3 +696,9 @@ int mailbox_seu_err_status(uint32_t *resp_buf, unsigned int resp_buf_len)
CMD_CASUAL, resp_buf, CMD_CASUAL, resp_buf,
&resp_buf_len); &resp_buf_len);
} }
int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len)
{
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SAFE_INJECT_SEU_ERR, arg, len,
CMD_CASUAL, NULL, NULL);
}

21
plat/intel/soc/common/socfpga_sip_svc.c
View file

@ -689,9 +689,19 @@ uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask)
} }
/* SDM SEU Error services */ /* SDM SEU Error services */
static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz) static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz)
{ {
if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) { if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) {
return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
}
return INTEL_SIP_SMC_STATUS_OK;
}
/* SDM SAFE SEU Error inject services */
static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len)
{
if (mailbox_safe_inject_seu_err(command, len) < 0) {
return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
} }
@ -714,7 +724,8 @@ uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
uint32_t retval = 0, completed_addr[3]; uint32_t retval = 0, completed_addr[3];
uint32_t retval2 = 0; uint32_t retval2 = 0;
uint32_t mbox_error = 0; uint32_t mbox_error = 0;
uint64_t retval64, rsu_respbuf[9], seu_respbuf[3]; uint64_t retval64, rsu_respbuf[9];
uint32_t seu_respbuf[3];
int status = INTEL_SIP_SMC_STATUS_OK; int status = INTEL_SIP_SMC_STATUS_OK;
int mbox_status; int mbox_status;
unsigned int len_in_resp; unsigned int len_in_resp;
@ -1229,6 +1240,10 @@ uintptr_t sip_smc_handler_v1(uint32_t smc_fid,
SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
} }
case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR:
status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
SMC_RET1(handle, status);
default: default:
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle, flags); cookie, handle, flags);