feat(mt8188): enable apusys mailbox mpu protect

Enable apusys mailbox mpu protect.

Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>

plat/mediatek/drivers/apusys/apusys.c

@@ -11,6 +11,7 @@
 #include "apusys.h"
 #include "apusys_devapc.h"
 #include "apusys_power.h"
+#include "apusys_rv.h"
 #include "apusys_security_ctrl_plat.h"
 #include <lib/mtk_init/mtk_init.h>
 #include <mtk_sip_svc.h>
@@ -54,6 +55,7 @@ int apusys_init(void)
 	}
 
 	apusys_security_ctrl_init();
+	apusys_rv_mbox_mpu_init();
 
 	return 0;
 }

plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+/* Vendor header */
+#include "apusys_rv.h"
+#include "apusys_rv_mbox_mpu.h"
+
+void apusys_rv_mbox_mpu_init(void)
+{
+	int i;
+
+	for (i = 0; i < APU_MBOX_NUM; i++) {
+		mmio_write_32(APU_MBOX_FUNC_CFG(i),
+			      (MBOX_CTRL_LOCK |
+			       (mbox_mpu_setting_tab[i].no_mpu << MBOX_NO_MPU_SHIFT)));
+		mmio_write_32(APU_MBOX_DOMAIN_CFG(i),
+			      (MBOX_CTRL_LOCK |
+			       (mbox_mpu_setting_tab[i].rx_ns << MBOX_RX_NS_SHIFT) |
+			       (mbox_mpu_setting_tab[i].rx_domain << MBOX_RX_DOMAIN_SHIFT) |
+			       (mbox_mpu_setting_tab[i].tx_ns << MBOX_TX_NS_SHIFT) |
+			       (mbox_mpu_setting_tab[i].tx_domain << MBOX_TX_DOMAIN_SHIFT)));
+	}
+}

plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_RV_H
+#define APUSYS_RV_H
+
+#include <platform_def.h>
+
+/* APU MBOX */
+#define MBOX_FUNC_CFG		(0xb0)
+#define MBOX_DOMAIN_CFG		(0xe0)
+#define MBOX_CTRL_LOCK		BIT(0)
+#define MBOX_NO_MPU_SHIFT	(16)
+#define MBOX_RX_NS_SHIFT	(16)
+#define MBOX_RX_DOMAIN_SHIFT	(17)
+#define MBOX_TX_NS_SHIFT	(24)
+#define MBOX_TX_DOMAIN_SHIFT	(25)
+#define MBOX_SIZE		(0x100)
+#define MBOX_NUM		(8)
+
+#define APU_MBOX(i)		(((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \
+						  (APU_MBOX1 + MBOX_SIZE * ((i) - MBOX_NUM)))
+#define APU_MBOX_FUNC_CFG(i)	(APU_MBOX(i) + MBOX_FUNC_CFG)
+#define APU_MBOX_DOMAIN_CFG(i)	(APU_MBOX(i) + MBOX_DOMAIN_CFG)
+
+void apusys_rv_mbox_mpu_init(void);
+
+#endif /* APUSYS_RV_H */

plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv_mbox_mpu.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_RV_MBOX_MPU_H
+#define APUSYS_RV_MBOX_MPU_H
+
+#define MPU_EN		(0)
+#define MPU_DIS		(1)
+#define MBOX0_TX_DOMAIN	(0)
+#define MBOX0_TX_NS	(1)
+#define MBOX4_RX_DOMAIN	(0)
+#define MBOX4_RX_NS	(0)
+#define MBOX5_TX_DOMAIN	(3)
+#define MBOX5_TX_NS	(0)
+#define MBOXN_RX_DOMAIN	(5)
+#define MBOXN_RX_NS	(1)
+#define MBOXN_TX_DOMAIN	(0)
+#define MBOXN_TX_NS	(0)
+
+struct mbox_mpu_setting {
+	uint32_t no_mpu;
+	uint32_t rx_ns;
+	uint32_t rx_domain;
+	uint32_t tx_ns;
+	uint32_t tx_domain;
+};
+
+static const struct mbox_mpu_setting mbox_mpu_setting_tab[] = {
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX0_TX_NS, MBOX0_TX_DOMAIN },
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+	{ MPU_DIS, MBOX4_RX_NS, MBOX4_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOX5_TX_NS, MBOX5_TX_DOMAIN },
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+	{ MPU_EN,  MBOXN_RX_NS, MBOXN_RX_DOMAIN, MBOXN_TX_NS, MBOXN_TX_DOMAIN },
+};
+
+#define APU_MBOX_NUM ARRAY_SIZE(mbox_mpu_setting_tab)
+
+#endif /* APUSYS_RV_MBOX_MPU_H */

plat/mediatek/drivers/apusys/apusys_rv/2.0/rules.mk

@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := apusys_rv_${MTK_SOC}
+
+PLAT_INCLUDES += -I${MTK_PLAT}/drivers/apusys/${MTK_SOC}
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_rv.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

plat/mediatek/drivers/apusys/rules.mk

@@ -10,11 +10,12 @@ MODULE := apusys
 
 LOCAL_SRCS-y:= ${LOCAL_DIR}/apusys.c
 
-PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC}
+PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC} -I${LOCAL_DIR}/apusys_rv/2.0
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
 
 SUB_RULES-y := ${LOCAL_DIR}/${MTK_SOC}
 SUB_RULES-y += ${LOCAL_DIR}/devapc
+SUB_RULES-y += ${LOCAL_DIR}/apusys_rv/2.0
 
 $(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))

plat/mediatek/mt8188/include/platform_def.h

@@ -31,6 +31,7 @@
 #define APU_RCX_CONFIG		(IO_PHYS + 0x09020000)
 #define APU_RCX_VCORE_CONFIG	(IO_PHYS + 0x090e0000)
 #define APU_MBOX0		(IO_PHYS + 0x090e1000)
+#define APU_MBOX1		(IO_PHYS + 0x090e2000)
 #define APU_RPCTOP		(IO_PHYS + 0x090f0000)
 #define APU_PCUTOP		(IO_PHYS + 0x090f1000)
 #define APU_AO_CTRL		(IO_PHYS + 0x090f2000)