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Merge changes I2c33105f,I010b3932 into integration

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* changes:
  feat(stm32mp25-fdts): update 2GB DDR configs
  feat(stm32mp25-fdts): enable WDQS for LPDDR4
This commit is contained in:
Govindraj Raja 2025-04-01 18:38:42 +02:00 • committed by TrustedFirmware Code Review
commit aac3e34f62
3 changed files with 44 additions and 36 deletions
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40
fdts/stm32mp25-ddr4-2x8Gbits-2x16bits-1200MHz.dtsi
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@ -1,19 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/* /*
* Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved * Copyright (C) 2022-2025, STMicroelectronics - All Rights Reserved
*/ */
/* /*
* STM32MP25 DDR4 board configuration * STM32MP25 DDR4 board configuration
* DDR4 2x8Gbits 2x16bits 1200MHz * DDR4 2x8Gbits 2x16bits 1200MHz
* *
* version 1 * version 2
* package 1 Package selection (14x14 and 18x18) * package 1 Package selection (14x14 and 18x18)
* memclk 1200MHz (2x DFI clock) + range check * memclk 1200MHz (2x DFI clock) + range check
* Speed_Bin Worse from JEDEC * Speed_Bin Worse from JEDEC
* device_width 16 x16 by default
* width 32 32: full width / 16: half width * width 32 32: full width / 16: half width
* ranks 1 Single or Dual rank * density 8Gbits (per device)
* density 8Gbits (per 16bit device)
* Addressing RBC row/bank interleaving * Addressing RBC row/bank interleaving
* RDBI No Read DBI * RDBI No Read DBI
*/ */
@ -49,6 +49,7 @@
#define DDR_INIT7 0x00000C16 #define DDR_INIT7 0x00000C16
#define DDR_DIMMCTL 0x00000000 #define DDR_DIMMCTL 0x00000000
#define DDR_RANKCTL 0x0000066F #define DDR_RANKCTL 0x0000066F
#define DDR_RANKCTL1 0x0000000D
#define DDR_DRAMTMG0 0x11152815 #define DDR_DRAMTMG0 0x11152815
#define DDR_DRAMTMG1 0x0004051E #define DDR_DRAMTMG1 0x0004051E
#define DDR_DRAMTMG2 0x0609060D #define DDR_DRAMTMG2 0x0609060D
@ -94,31 +95,34 @@
#define DDR_ADDRMAP11 0x00000007 #define DDR_ADDRMAP11 0x00000007
#define DDR_ODTCFG 0x06000618 #define DDR_ODTCFG 0x06000618
#define DDR_ODTMAP 0x00000001 #define DDR_ODTMAP 0x00000001
#define DDR_SCHED 0x00000F00 #define DDR_SCHED 0x80001B00
#define DDR_SCHED1 0x00000000 #define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x0F000001 #define DDR_PERFHPR1 0x04000200
#define DDR_PERFLPR1 0x0F000080 #define DDR_PERFLPR1 0x08000080
#define DDR_PERFWR1 0x01000200 #define DDR_PERFWR1 0x08000400
#define DDR_SCHED3 0x04040208
#define DDR_SCHED4 0x08400810
#define DDR_DBG0 0x00000000 #define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000 #define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000 #define DDR_DBGCMD 0x00000000
#define DDR_SWCTL 0x00000000 #define DDR_SWCTL 0x00000000
#define DDR_SWCTLSTATIC 0x00000000
#define DDR_POISONCFG 0x00000000 #define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000000 #define DDR_PCCFG 0x00000000
#define DDR_PCFGR_0 0x00004100 #define DDR_PCFGR_0 0x00704100
#define DDR_PCFGW_0 0x00004100 #define DDR_PCFGW_0 0x00004100
#define DDR_PCTRL_0 0x00000000 #define DDR_PCTRL_0 0x00000000
#define DDR_PCFGQOS0_0 0x00200007 #define DDR_PCFGQOS0_0 0x0021000C
#define DDR_PCFGQOS1_0 0x01000100 #define DDR_PCFGQOS1_0 0x01000080
#define DDR_PCFGWQOS0_0 0x00000C07 #define DDR_PCFGWQOS0_0 0x01100C07
#define DDR_PCFGWQOS1_0 0x02000200 #define DDR_PCFGWQOS1_0 0x04000200
#define DDR_PCFGR_1 0x00004100 #define DDR_PCFGR_1 0x00704100
#define DDR_PCFGW_1 0x00004100 #define DDR_PCFGW_1 0x00004100
#define DDR_PCTRL_1 0x00000000 #define DDR_PCTRL_1 0x00000000
#define DDR_PCFGQOS0_1 0x00200007 #define DDR_PCFGQOS0_1 0x00100007
#define DDR_PCFGQOS1_1 0x01000180 #define DDR_PCFGQOS1_1 0x01000080
#define DDR_PCFGWQOS0_1 0x00000C07 #define DDR_PCFGWQOS0_1 0x01100C07
#define DDR_PCFGWQOS1_1 0x04000400 #define DDR_PCFGWQOS1_1 0x04000200
#define DDR_UIB_DRAMTYPE 0x00000000 #define DDR_UIB_DRAMTYPE 0x00000000
#define DDR_UIB_DIMMTYPE 0x00000004 #define DDR_UIB_DIMMTYPE 0x00000004

26
fdts/stm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi
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@ -7,7 +7,7 @@
* STM32MP25 LPDDR4 board configuration * STM32MP25 LPDDR4 board configuration
* LPDDR4 1x16Gbits 1x32bits 1200MHz * LPDDR4 1x16Gbits 1x32bits 1200MHz
* *
* version 1 * version 2
* memclk 1200MHz (2x DFI clock) * memclk 1200MHz (2x DFI clock)
* width 32 32: full width / 16: half width * width 32 32: full width / 16: half width
* ranks 1 Single or Dual rank * ranks 1 Single or Dual rank
@ -46,10 +46,11 @@
#define DDR_INIT3 0x00C40024 #define DDR_INIT3 0x00C40024
#define DDR_INIT4 0x00310008 #define DDR_INIT4 0x00310008
#define DDR_INIT5 0x00100004 #define DDR_INIT5 0x00100004
#define DDR_INIT6 0x00660050 #define DDR_INIT6 0x00660047
#define DDR_INIT7 0x00050019 #define DDR_INIT7 0x00050047
#define DDR_DIMMCTL 0x00000000 #define DDR_DIMMCTL 0x00000000
#define DDR_RANKCTL 0x0000066F #define DDR_RANKCTL 0x0000066F
#define DDR_RANKCTL1 0x00000011
#define DDR_DRAMTMG0 0x1718141A #define DDR_DRAMTMG0 0x1718141A
#define DDR_DRAMTMG1 0x00050524 #define DDR_DRAMTMG1 0x00050524
#define DDR_DRAMTMG2 0x060C1111 #define DDR_DRAMTMG2 0x060C1111
@ -95,25 +96,28 @@
#define DDR_ADDRMAP11 0x00000007 #define DDR_ADDRMAP11 0x00000007
#define DDR_ODTCFG 0x04000400 #define DDR_ODTCFG 0x04000400
#define DDR_ODTMAP 0x00000000 #define DDR_ODTMAP 0x00000000
#define DDR_SCHED 0x00001B00 #define DDR_SCHED 0x80001B00
#define DDR_SCHED1 0x00000000 #define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x04000200 #define DDR_PERFHPR1 0x04000200
#define DDR_PERFLPR1 0x08000080 #define DDR_PERFLPR1 0x08000080
#define DDR_PERFWR1 0x08000400 #define DDR_PERFWR1 0x08000400
#define DDR_SCHED3 0x04040208
#define DDR_SCHED4 0x08400810
#define DDR_DBG0 0x00000000 #define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000 #define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000 #define DDR_DBGCMD 0x00000000
#define DDR_SWCTL 0x00000000 #define DDR_SWCTL 0x00000000
#define DDR_SWCTLSTATIC 0x00000000
#define DDR_POISONCFG 0x00000000 #define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000000 #define DDR_PCCFG 0x00000000
#define DDR_PCFGR_0 0x00004100 #define DDR_PCFGR_0 0x00704100
#define DDR_PCFGW_0 0x00004100 #define DDR_PCFGW_0 0x00004100
#define DDR_PCTRL_0 0x00000000 #define DDR_PCTRL_0 0x00000000
#define DDR_PCFGQOS0_0 0x0021000C #define DDR_PCFGQOS0_0 0x0021000C
#define DDR_PCFGQOS1_0 0x01000080 #define DDR_PCFGQOS1_0 0x01000080
#define DDR_PCFGWQOS0_0 0x01100C07 #define DDR_PCFGWQOS0_0 0x01100C07
#define DDR_PCFGWQOS1_0 0x04000200 #define DDR_PCFGWQOS1_0 0x04000200
#define DDR_PCFGR_1 0x00004100 #define DDR_PCFGR_1 0x00704100
#define DDR_PCFGW_1 0x00004100 #define DDR_PCFGW_1 0x00004100
#define DDR_PCTRL_1 0x00000000 #define DDR_PCTRL_1 0x00000000
#define DDR_PCFGQOS0_1 0x00100007 #define DDR_PCFGQOS0_1 0x00100007
@ -148,8 +152,8 @@
#define DDR_UIA_EXTCALRESVAL 0x00000000 #define DDR_UIA_EXTCALRESVAL 0x00000000
#define DDR_UIA_IS2TTIMING_0 0x00000000 #define DDR_UIA_IS2TTIMING_0 0x00000000
#define DDR_UIA_ODTIMPEDANCE_0 0x00000035 #define DDR_UIA_ODTIMPEDANCE_0 0x00000035
#define DDR_UIA_TXIMPEDANCE_0 0x0000003C #define DDR_UIA_TXIMPEDANCE_0 0x00000028
#define DDR_UIA_ATXIMPEDANCE 0x0000001E #define DDR_UIA_ATXIMPEDANCE 0x00000028
#define DDR_UIA_MEMALERTEN 0x00000000 #define DDR_UIA_MEMALERTEN 0x00000000
#define DDR_UIA_MEMALERTPUIMP 0x00000000 #define DDR_UIA_MEMALERTPUIMP 0x00000000
#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000 #define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
@ -157,7 +161,7 @@
#define DDR_UIA_DISDYNADRTRI_0 0x00000001 #define DDR_UIA_DISDYNADRTRI_0 0x00000001
#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A #define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A
#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005 #define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005
#define DDR_UIA_WDQSEXT 0x00000000 #define DDR_UIA_WDQSEXT 0x00000001
#define DDR_UIA_CALINTERVAL 0x00000009 #define DDR_UIA_CALINTERVAL 0x00000009
#define DDR_UIA_CALONCE 0x00000000 #define DDR_UIA_CALONCE 0x00000000
#define DDR_UIA_LP4RL_0 0x00000004 #define DDR_UIA_LP4RL_0 0x00000004
@ -193,9 +197,9 @@
#define DDR_UIM_MR5_0 0x00000000 #define DDR_UIM_MR5_0 0x00000000
#define DDR_UIM_MR6_0 0x00000000 #define DDR_UIM_MR6_0 0x00000000
#define DDR_UIM_MR11_0 0x00000066 #define DDR_UIM_MR11_0 0x00000066
#define DDR_UIM_MR12_0 0x00000050 #define DDR_UIM_MR12_0 0x00000047
#define DDR_UIM_MR13_0 0x00000008 #define DDR_UIM_MR13_0 0x00000008
#define DDR_UIM_MR14_0 0x00000019 #define DDR_UIM_MR14_0 0x00000047
#define DDR_UIM_MR22_0 0x00000005 #define DDR_UIM_MR22_0 0x00000005
#define DDR_UIS_SWIZZLE_0 0x00000003 #define DDR_UIS_SWIZZLE_0 0x00000003

2
fdts/stm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi
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@ -161,7 +161,7 @@
#define DDR_UIA_DISDYNADRTRI_0 0x00000001 #define DDR_UIA_DISDYNADRTRI_0 0x00000001
#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A #define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A
#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005 #define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005
#define DDR_UIA_WDQSEXT 0x00000000 #define DDR_UIA_WDQSEXT 0x00000001
#define DDR_UIA_CALINTERVAL 0x00000009 #define DDR_UIA_CALINTERVAL 0x00000009
#define DDR_UIA_CALONCE 0x00000000 #define DDR_UIA_CALONCE 0x00000000
#define DDR_UIA_LP4RL_0 0x00000004 #define DDR_UIA_LP4RL_0 0x00000004