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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(stm32mp25-fdts): update 2GB DDR configs
Update the 2GB LpDDR4 and DDR4 DT settings. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> Change-Id: I2c33105f31364ff15a66a0749b2400dd69db33e3
This commit is contained in:
Nicolas Le Bayon
Yann Gautier
parent
29917d3a12
commit
388cb47cf0
2 changed files with 43 additions and 35 deletions
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@ -1,21 +1,21 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
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* Copyright (C) 2022-2025, STMicroelectronics - All Rights Reserved
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*/
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/*
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* STM32MP25 DDR4 board configuration
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* DDR4 2x8Gbits 2x16bits 1200MHz
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*
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* version 1
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* package 1 Package selection (14x14 and 18x18)
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* memclk 1200MHz (2x DFI clock) + range check
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* Speed_Bin Worse from JEDEC
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* width 32 32: full width / 16: half width
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* ranks 1 Single or Dual rank
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* density 8Gbits (per 16bit device)
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* Addressing RBC row/bank interleaving
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* RDBI No Read DBI
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* version 2
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* package 1 Package selection (14x14 and 18x18)
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* memclk 1200MHz (2x DFI clock) + range check
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* Speed_Bin Worse from JEDEC
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* device_width 16 x16 by default
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* width 32 32: full width / 16: half width
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* density 8Gbits (per device)
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* Addressing RBC row/bank interleaving
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* RDBI No Read DBI
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*/
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#define DDR_MEM_NAME "DDR4 2x8Gbits 2x16bits 1200MHz"
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@ -49,6 +49,7 @@
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#define DDR_INIT7 0x00000C16
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#define DDR_DIMMCTL 0x00000000
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#define DDR_RANKCTL 0x0000066F
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#define DDR_RANKCTL1 0x0000000D
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#define DDR_DRAMTMG0 0x11152815
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#define DDR_DRAMTMG1 0x0004051E
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#define DDR_DRAMTMG2 0x0609060D
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@ -94,31 +95,34 @@
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#define DDR_ADDRMAP11 0x00000007
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#define DDR_ODTCFG 0x06000618
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000F00
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#define DDR_SCHED 0x80001B00
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x0F000001
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#define DDR_PERFLPR1 0x0F000080
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#define DDR_PERFWR1 0x01000200
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#define DDR_PERFHPR1 0x04000200
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#define DDR_PERFLPR1 0x08000080
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#define DDR_PERFWR1 0x08000400
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#define DDR_SCHED3 0x04040208
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#define DDR_SCHED4 0x08400810
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_SWCTL 0x00000000
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#define DDR_SWCTLSTATIC 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000000
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#define DDR_PCFGR_0 0x00004100
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#define DDR_PCFGR_0 0x00704100
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#define DDR_PCFGW_0 0x00004100
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#define DDR_PCTRL_0 0x00000000
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#define DDR_PCFGQOS0_0 0x00200007
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#define DDR_PCFGQOS1_0 0x01000100
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#define DDR_PCFGWQOS0_0 0x00000C07
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#define DDR_PCFGWQOS1_0 0x02000200
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#define DDR_PCFGR_1 0x00004100
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#define DDR_PCFGQOS0_0 0x0021000C
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#define DDR_PCFGQOS1_0 0x01000080
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#define DDR_PCFGWQOS0_0 0x01100C07
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#define DDR_PCFGWQOS1_0 0x04000200
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#define DDR_PCFGR_1 0x00704100
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#define DDR_PCFGW_1 0x00004100
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#define DDR_PCTRL_1 0x00000000
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#define DDR_PCFGQOS0_1 0x00200007
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#define DDR_PCFGQOS1_1 0x01000180
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#define DDR_PCFGWQOS0_1 0x00000C07
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#define DDR_PCFGWQOS1_1 0x04000400
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#define DDR_PCFGQOS0_1 0x00100007
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#define DDR_PCFGQOS1_1 0x01000080
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#define DDR_PCFGWQOS0_1 0x01100C07
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#define DDR_PCFGWQOS1_1 0x04000200
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#define DDR_UIB_DRAMTYPE 0x00000000
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#define DDR_UIB_DIMMTYPE 0x00000004
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@ -7,7 +7,7 @@
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* STM32MP25 LPDDR4 board configuration
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* LPDDR4 1x16Gbits 1x32bits 1200MHz
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*
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* version 1
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* version 2
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* memclk 1200MHz (2x DFI clock)
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* width 32 32: full width / 16: half width
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* ranks 1 Single or Dual rank
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@ -46,10 +46,11 @@
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#define DDR_INIT3 0x00C40024
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#define DDR_INIT4 0x00310008
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#define DDR_INIT5 0x00100004
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#define DDR_INIT6 0x00660050
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#define DDR_INIT7 0x00050019
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#define DDR_INIT6 0x00660047
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#define DDR_INIT7 0x00050047
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#define DDR_DIMMCTL 0x00000000
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#define DDR_RANKCTL 0x0000066F
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#define DDR_RANKCTL1 0x00000011
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#define DDR_DRAMTMG0 0x1718141A
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#define DDR_DRAMTMG1 0x00050524
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#define DDR_DRAMTMG2 0x060C1111
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@ -95,25 +96,28 @@
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#define DDR_ADDRMAP11 0x00000007
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#define DDR_ODTCFG 0x04000400
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#define DDR_ODTMAP 0x00000000
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#define DDR_SCHED 0x00001B00
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#define DDR_SCHED 0x80001B00
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x04000200
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#define DDR_PERFLPR1 0x08000080
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#define DDR_PERFWR1 0x08000400
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#define DDR_SCHED3 0x04040208
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#define DDR_SCHED4 0x08400810
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_SWCTL 0x00000000
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#define DDR_SWCTLSTATIC 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000000
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#define DDR_PCFGR_0 0x00004100
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#define DDR_PCFGR_0 0x00704100
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#define DDR_PCFGW_0 0x00004100
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#define DDR_PCTRL_0 0x00000000
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#define DDR_PCFGQOS0_0 0x0021000C
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#define DDR_PCFGQOS1_0 0x01000080
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#define DDR_PCFGWQOS0_0 0x01100C07
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#define DDR_PCFGWQOS1_0 0x04000200
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#define DDR_PCFGR_1 0x00004100
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#define DDR_PCFGR_1 0x00704100
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#define DDR_PCFGW_1 0x00004100
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#define DDR_PCTRL_1 0x00000000
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#define DDR_PCFGQOS0_1 0x00100007
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@ -148,8 +152,8 @@
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#define DDR_UIA_EXTCALRESVAL 0x00000000
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#define DDR_UIA_IS2TTIMING_0 0x00000000
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#define DDR_UIA_ODTIMPEDANCE_0 0x00000035
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#define DDR_UIA_TXIMPEDANCE_0 0x0000003C
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#define DDR_UIA_ATXIMPEDANCE 0x0000001E
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#define DDR_UIA_TXIMPEDANCE_0 0x00000028
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#define DDR_UIA_ATXIMPEDANCE 0x00000028
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#define DDR_UIA_MEMALERTEN 0x00000000
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#define DDR_UIA_MEMALERTPUIMP 0x00000000
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#define DDR_UIA_MEMALERTVREFLEVEL 0x00000000
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#define DDR_UIA_DISDYNADRTRI_0 0x00000001
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#define DDR_UIA_PHYMSTRTRAININTERVAL_0 0x0000000A
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#define DDR_UIA_PHYMSTRMAXREQTOACK_0 0x00000005
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#define DDR_UIA_WDQSEXT 0x00000000
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#define DDR_UIA_WDQSEXT 0x00000001
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#define DDR_UIA_CALINTERVAL 0x00000009
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#define DDR_UIA_CALONCE 0x00000000
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#define DDR_UIA_LP4RL_0 0x00000004
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@ -193,9 +197,9 @@
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#define DDR_UIM_MR5_0 0x00000000
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#define DDR_UIM_MR6_0 0x00000000
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#define DDR_UIM_MR11_0 0x00000066
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#define DDR_UIM_MR12_0 0x00000050
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#define DDR_UIM_MR12_0 0x00000047
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#define DDR_UIM_MR13_0 0x00000008
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#define DDR_UIM_MR14_0 0x00000019
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#define DDR_UIM_MR14_0 0x00000047
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#define DDR_UIM_MR22_0 0x00000005
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#define DDR_UIS_SWIZZLE_0 0x00000003
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