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refactor(neoverse-rd): unify GIC SPI range macros

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The existing macros representing GIC SPI minimum and maximum for
multichip platforms lack a consistent naming convention. To address
this, establish the convention "NRD_CHIP<x>_SPI_MIN" and
"NRD_CHIP<x>_SPI_MAX" for use across all Neoverse Reference Design
multichip platforms.

Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce
similar macros.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23
This commit is contained in:
Rohit Mathew 2024-02-26 20:39:04 +00:00
parent a0bd619859
commit a965d73f02
6 changed files with 40 additions and 12 deletions
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5
plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
View file

@ -37,7 +37,8 @@
#define PLAT_ARM_GICD_BASE UL(0x30000000) #define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICR_BASE UL(0x300C0000) #define PLAT_ARM_GICR_BASE UL(0x300C0000)
#define RDN1E1_CHIP0_SPI_START U(32) /* GIC SPI range for multichip */
#define RDN1E1_CHIP0_SPI_END U(991) #define NRD_CHIP0_SPI_MIN U(32)
#define NRD_CHIP0_SPI_MAX U(991)
#endif /* PLATFORM_DEF_H */ #endif /* PLATFORM_DEF_H */

5
plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
View file

@ -27,8 +27,9 @@ static struct gic600_multichip_data rdn1e1_multichip_data __init = {
(PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16 (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
}, },
.spi_ids = { .spi_ids = {
{PLAT_ARM_GICD_BASE, RDN1E1_CHIP0_SPI_START, {PLAT_ARM_GICD_BASE,
RDN1E1_CHIP0_SPI_END}, NRD_CHIP0_SPI_MIN,
NRD_CHIP0_SPI_MAX},
{0, 0, 0} {0, 0, 0}
} }
}; };

16
plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h
View file

@ -74,4 +74,20 @@
#define NRD_ADDR_BITS_PER_CHIP U(42) /* 4TB */ #define NRD_ADDR_BITS_PER_CHIP U(42) /* 4TB */
#endif #endif
/* GIC SPI range for multichip */
#define NRD_CHIP0_SPI_MIN U(32)
#define NRD_CHIP0_SPI_MAX U(511)
#if NRD_CHIP_COUNT > 1
#define NRD_CHIP1_SPI_MIN U(512)
#define NRD_CHIP1_SPI_MAX U(991)
#endif
#if NRD_CHIP_COUNT > 2
#define NRD_CHIP2_SPI_MIN U(4096)
#define NRD_CHIP2_SPI_MAX U(4575)
#endif
#if NRD_CHIP_COUNT > 3
#define NRD_CHIP3_SPI_MIN U(4576)
#define NRD_CHIP3_SPI_MAX U(5055)
#endif
#endif /* PLATFORM_DEF_H */ #endif /* PLATFORM_DEF_H */

16
plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c
View file

@ -49,15 +49,23 @@ static struct gic600_multichip_data rdn2mc_multichip_data __init = {
#endif #endif
}, },
.spi_ids = { .spi_ids = {
{PLAT_ARM_GICD_BASE, 32, 511}, {PLAT_ARM_GICD_BASE,
NRD_CHIP0_SPI_MIN,
NRD_CHIP0_SPI_MAX},
#if NRD_CHIP_COUNT > 1 #if NRD_CHIP_COUNT > 1
{PLAT_ARM_GICD_BASE, 512, 991}, {PLAT_ARM_GICD_BASE,
NRD_CHIP1_SPI_MIN,
NRD_CHIP1_SPI_MAX},
#endif #endif
#if NRD_CHIP_COUNT > 2 #if NRD_CHIP_COUNT > 2
{PLAT_ARM_GICD_BASE, 4096, 4575}, {PLAT_ARM_GICD_BASE,
NRD_CHIP2_SPI_MIN,
NRD_CHIP2_SPI_MAX},
#endif #endif
#if NRD_CHIP_COUNT > 3 #if NRD_CHIP_COUNT > 3
{PLAT_ARM_GICD_BASE, 4576, 5055}, {PLAT_ARM_GICD_BASE,
NRD_CHIP3_SPI_MIN,
NRD_CHIP3_SPI_MAX},
#endif #endif
} }
}; };

5
plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
View file

@ -56,7 +56,8 @@
#define PLAT_ARM_GICD_BASE UL(0x30000000) #define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICR_BASE UL(0x30140000) #define PLAT_ARM_GICR_BASE UL(0x30140000)
#define RDV1MC_CHIP0_SPI_START U(32) /* GIC SPI range for multichip */
#define RDV1MC_CHIP0_SPI_END U(991) #define NRD_CHIP0_SPI_MIN U(32)
#define NRD_CHIP0_SPI_MAX U(991)
#endif /* PLATFORM_DEF_H */ #endif /* PLATFORM_DEF_H */

5
plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
View file

@ -43,8 +43,9 @@ static struct gic600_multichip_data rdv1mc_multichip_data __init = {
#endif #endif
}, },
.spi_ids = { .spi_ids = {
{PLAT_ARM_GICD_BASE, RDV1MC_CHIP0_SPI_START, {PLAT_ARM_GICD_BASE,
RDV1MC_CHIP0_SPI_END}, NRD_CHIP0_SPI_MIN,
NRD_CHIP0_SPI_MAX},
{0, 0, 0}, {0, 0, 0},
#if (NRD_CHIP_COUNT > 2) #if (NRD_CHIP_COUNT > 2)
{0, 0, 0}, {0, 0, 0},