From a965d73f02d0f197debd7436b4a0d34fcd2da85b Mon Sep 17 00:00:00 2001 From: Rohit Mathew Date: Mon, 26 Feb 2024 20:39:04 +0000 Subject: [PATCH] refactor(neoverse-rd): unify GIC SPI range macros The existing macros representing GIC SPI minimum and maximum for multichip platforms lack a consistent naming convention. To address this, establish the convention "NRD_CHIP_SPI_MIN" and "NRD_CHIP_SPI_MAX" for use across all Neoverse Reference Design multichip platforms. Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce similar macros. Signed-off-by: Rohit Mathew Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23 --- .../platform/rdn1edge/include/platform_def.h | 5 +++-- .../platform/rdn1edge/rdn1edge_plat.c | 5 +++-- .../platform/rdn2/include/platform_def.h | 16 ++++++++++++++++ .../board/neoverse_rd/platform/rdn2/rdn2_plat.c | 16 ++++++++++++---- .../platform/rdv1mc/include/platform_def.h | 5 +++-- .../neoverse_rd/platform/rdv1mc/rdv1mc_plat.c | 5 +++-- 6 files changed, 40 insertions(+), 12 deletions(-) diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h index 5c27fc318..5357c31e0 100644 --- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h +++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h @@ -37,7 +37,8 @@ #define PLAT_ARM_GICD_BASE UL(0x30000000) #define PLAT_ARM_GICR_BASE UL(0x300C0000) -#define RDN1E1_CHIP0_SPI_START U(32) -#define RDN1E1_CHIP0_SPI_END U(991) +/* GIC SPI range for multichip */ +#define NRD_CHIP0_SPI_MIN U(32) +#define NRD_CHIP0_SPI_MAX U(991) #endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c index 1a6bed6e2..ccabe2293 100644 --- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c +++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c @@ -27,8 +27,9 @@ static struct gic600_multichip_data rdn1e1_multichip_data __init = { (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16 }, .spi_ids = { - {PLAT_ARM_GICD_BASE, RDN1E1_CHIP0_SPI_START, - RDN1E1_CHIP0_SPI_END}, + {PLAT_ARM_GICD_BASE, + NRD_CHIP0_SPI_MIN, + NRD_CHIP0_SPI_MAX}, {0, 0, 0} } }; diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h index c119e9f60..f6f2b862d 100644 --- a/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h +++ b/plat/arm/board/neoverse_rd/platform/rdn2/include/platform_def.h @@ -74,4 +74,20 @@ #define NRD_ADDR_BITS_PER_CHIP U(42) /* 4TB */ #endif +/* GIC SPI range for multichip */ +#define NRD_CHIP0_SPI_MIN U(32) +#define NRD_CHIP0_SPI_MAX U(511) +#if NRD_CHIP_COUNT > 1 +#define NRD_CHIP1_SPI_MIN U(512) +#define NRD_CHIP1_SPI_MAX U(991) +#endif +#if NRD_CHIP_COUNT > 2 +#define NRD_CHIP2_SPI_MIN U(4096) +#define NRD_CHIP2_SPI_MAX U(4575) +#endif +#if NRD_CHIP_COUNT > 3 +#define NRD_CHIP3_SPI_MIN U(4576) +#define NRD_CHIP3_SPI_MAX U(5055) +#endif + #endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c index 74596793d..b1046d69b 100644 --- a/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c +++ b/plat/arm/board/neoverse_rd/platform/rdn2/rdn2_plat.c @@ -49,15 +49,23 @@ static struct gic600_multichip_data rdn2mc_multichip_data __init = { #endif }, .spi_ids = { - {PLAT_ARM_GICD_BASE, 32, 511}, + {PLAT_ARM_GICD_BASE, + NRD_CHIP0_SPI_MIN, + NRD_CHIP0_SPI_MAX}, #if NRD_CHIP_COUNT > 1 - {PLAT_ARM_GICD_BASE, 512, 991}, + {PLAT_ARM_GICD_BASE, + NRD_CHIP1_SPI_MIN, + NRD_CHIP1_SPI_MAX}, #endif #if NRD_CHIP_COUNT > 2 - {PLAT_ARM_GICD_BASE, 4096, 4575}, + {PLAT_ARM_GICD_BASE, + NRD_CHIP2_SPI_MIN, + NRD_CHIP2_SPI_MAX}, #endif #if NRD_CHIP_COUNT > 3 - {PLAT_ARM_GICD_BASE, 4576, 5055}, + {PLAT_ARM_GICD_BASE, + NRD_CHIP3_SPI_MIN, + NRD_CHIP3_SPI_MAX}, #endif } }; diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h index 2cec57c47..b4c5c0a2e 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h +++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h @@ -56,7 +56,8 @@ #define PLAT_ARM_GICD_BASE UL(0x30000000) #define PLAT_ARM_GICR_BASE UL(0x30140000) -#define RDV1MC_CHIP0_SPI_START U(32) -#define RDV1MC_CHIP0_SPI_END U(991) +/* GIC SPI range for multichip */ +#define NRD_CHIP0_SPI_MIN U(32) +#define NRD_CHIP0_SPI_MAX U(991) #endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c index e316a1c3c..5713cb9ab 100644 --- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c +++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c @@ -43,8 +43,9 @@ static struct gic600_multichip_data rdv1mc_multichip_data __init = { #endif }, .spi_ids = { - {PLAT_ARM_GICD_BASE, RDV1MC_CHIP0_SPI_START, - RDV1MC_CHIP0_SPI_END}, + {PLAT_ARM_GICD_BASE, + NRD_CHIP0_SPI_MIN, + NRD_CHIP0_SPI_MAX}, {0, 0, 0}, #if (NRD_CHIP_COUNT > 2) {0, 0, 0},