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Merge pull request #1168 from matt2048/master

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Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS
This commit is contained in:
davidcunado-arm 2017-12-04 22:39:40 +00:00 • committed by GitHub
commit a852ec4605
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GPG key ID: 4AEE18F83AFDEB23
4 changed files with 6 additions and 9 deletions
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4
lib/cpus/aarch32/cortex_a53.S
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@ -174,7 +174,7 @@ func cortex_a53_core_pwr_dwn
push {r12, lr}
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
@ -204,7 +204,7 @@ func cortex_a53_cluster_pwr_dwn
push {r12, lr}
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)

4
lib/cpus/aarch32/cortex_a57.S
View file

@ -406,7 +406,7 @@ func cortex_a57_core_pwr_dwn
push {r12, lr}
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
@ -448,7 +448,7 @@ func cortex_a57_cluster_pwr_dwn
push {r12, lr}
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)

4
lib/cpus/aarch32/cortex_a72.S
View file

@ -120,7 +120,7 @@ func cortex_a72_core_pwr_dwn
push {r12, lr}
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
@ -167,7 +167,7 @@ func cortex_a72_cluster_pwr_dwn
push {r12, lr}
/* Assert if cache is enabled */
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)

3
make_helpers/defaults.mk
View file

@ -24,9 +24,6 @@ ARM_ARCH_MINOR := 0
# in EL3. The platform port can change this value if needed.
ARM_GIC_ARCH := 2
# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
ASM_ASSERTION := 0
# Base commit to perform code check on
BASE_COMMIT := origin/master