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Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS
This patch replaces the macro ASM_ASSERTION with the macro ENABLE_ASSERTIONS in ARM Cortex-A53/57/72 MPCore Processor related files. There is build error when ASM_ASSERTION is set to 1 and ENABLE_ASSERTIONS is set to 0 because function asm_assert in common/aarch32/debug.S is defined in the macro ENABLE_ASSERTIONS but is called with the macro ASM_ASSERTION. There is also the indication to use ENABLE_ASSERTIONS but not ASM_ASSERTION in the Makefile. Signed-off-by: Matt Ma <matt.ma@spreadtrum.com>
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parent
203444c500
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4 changed files with 6 additions and 9 deletions
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@ -174,7 +174,7 @@ func cortex_a53_core_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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@ -204,7 +204,7 @@ func cortex_a53_cluster_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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@ -406,7 +406,7 @@ func cortex_a57_core_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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@ -448,7 +448,7 @@ func cortex_a57_cluster_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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@ -120,7 +120,7 @@ func cortex_a72_core_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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@ -167,7 +167,7 @@ func cortex_a72_cluster_pwr_dwn
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push {r12, lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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@ -24,9 +24,6 @@ ARM_ARCH_MINOR := 0
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# in EL3. The platform port can change this value if needed.
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ARM_GIC_ARCH := 2
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# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
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ASM_ASSERTION := 0
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# Base commit to perform code check on
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BASE_COMMIT := origin/master
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