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fix(zynqmp): modify conditions to have boolean type

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This corrects the MISRA violation C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially
boolean type.
Updated controlling expression to explicitly compare with zero.

Change-Id: I5bf7070db9bced50f5d37a3d9406301585930b50
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This commit is contained in:
Maheedhar Bollapalli 2024-04-22 15:10:45 +05:30
parent 7e9d2a56e7
commit a42e6e44b8
7 changed files with 12 additions and 12 deletions
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6
plat/xilinx/zynqmp/plat_psci.c
View file

@ -169,7 +169,7 @@ static void __dead2 zynqmp_system_off(void)
pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN, pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope()); pm_get_shutdown_scope());
while (1) { while (true) {
wfi(); wfi();
} }
} }
@ -183,7 +183,7 @@ static void __dead2 zynqmp_system_reset(void)
pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
pm_get_shutdown_scope()); pm_get_shutdown_scope());
while (1) { while (true) {
wfi(); wfi();
} }
} }
@ -204,7 +204,7 @@ static int32_t zynqmp_validate_power_state(uint32_t power_state,
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
} }
/* We expect the 'state id' to be zero */ /* We expect the 'state id' to be zero */
if (psci_get_pstate_id(power_state)) { if (psci_get_pstate_id(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS; return PSCI_E_INVALID_PARAMS;
} }

2
plat/xilinx/zynqmp/plat_zynqmp.c
View file

@ -10,7 +10,7 @@
int32_t plat_core_pos_by_mpidr(u_register_t mpidr) int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
{ {
if (mpidr & MPIDR_CLUSTER_MASK) { if ((mpidr & MPIDR_CLUSTER_MASK) != 0U) {
return -1; return -1;
} }

4
plat/xilinx/zynqmp/pm_service/pm_api_clock.c
View file

@ -2684,8 +2684,8 @@ enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id,
nodes = *clocks[clock_id].nodes; nodes = *clocks[clock_id].nodes;
for (i = 0; i < clocks[clock_id].num_nodes; i++) { for (i = 0; i < clocks[clock_id].num_nodes; i++) {
if (nodes[i].type == div_type) { if (nodes[i].type == div_type) {
if (CLK_DIVIDER_POWER_OF_TWO & if ((CLK_DIVIDER_POWER_OF_TWO &
nodes[i].typeflags) { nodes[i].typeflags) != 0U) {
*max_div = (1U << (BIT(nodes[i].width) - 1U)); *max_div = (1U << (BIT(nodes[i].width) - 1U));
} else { } else {
*max_div = BIT(nodes[i].width) - 1U; *max_div = BIT(nodes[i].width) - 1U;

2
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
View file

@ -62,7 +62,7 @@ static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(uint32_t mode)
{ {
uint32_t val; uint32_t val;
if (mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) { if ((mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) != 0U) {
return PM_RET_ERROR_ACCESS; return PM_RET_ERROR_ACCESS;
} }

2
plat/xilinx/zynqmp/pm_service/pm_client.c
View file

@ -204,7 +204,7 @@ static void pm_client_set_wakeup_sources(void)
continue; continue;
} }
while (reg) { while (reg != 0U) {
enum pm_node_id node; enum pm_node_id node;
uint32_t idx, ret, irq, lowest_set = reg & (-reg); uint32_t idx, ret, irq, lowest_set = reg & (-reg);

6
plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
View file

@ -1115,7 +1115,7 @@ static enum pm_ret_status pm_clock_gate(uint32_t clock_id,
return status; return status;
} }
if (enable) { if (enable != 0U) {
api_id = PM_CLOCK_ENABLE; api_id = PM_CLOCK_ENABLE;
} else { } else {
api_id = PM_CLOCK_DISABLE; api_id = PM_CLOCK_DISABLE;
@ -1297,7 +1297,7 @@ enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
return status; return status;
} }
if (pm_clock_has_div(clock_id, PM_CLOCK_DIV0_ID)) { if ((pm_clock_has_div(clock_id, PM_CLOCK_DIV0_ID)) != 0U) {
/* Send request to the PMU to get div0 */ /* Send request to the PMU to get div0 */
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id, PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
PM_CLOCK_DIV0_ID); PM_CLOCK_DIV0_ID);
@ -1308,7 +1308,7 @@ enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
*divider = val; *divider = val;
} }
if (pm_clock_has_div(clock_id, PM_CLOCK_DIV1_ID)) { if ((pm_clock_has_div(clock_id, PM_CLOCK_DIV1_ID)) != 0U) {
/* Send request to the PMU to get div1 */ /* Send request to the PMU to get div1 */
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id, PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
PM_CLOCK_DIV1_ID); PM_CLOCK_DIV1_ID);

2
plat/xilinx/zynqmp/sip_svc_setup.c
View file

@ -81,7 +81,7 @@ static uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n", VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4); smc_fid, x1, x2, x3, x4);
if (smc_fid & SIP_FID_MASK) { if ((smc_fid & (uint32_t)SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid); WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK); SMC_RET1(handle, SMC_UNK);
} }