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fix(versal2): ospi data integrity cases are failing

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Value of linear mode is in bit 1 and not in bit 0.
Updated logic to clear and set bit 1 for linear mode.

Change-Id: Ia39b2a1b2e35f02edd36e043045b568d231745ba
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This commit is contained in:
Maheedhar Bollapalli 2024-10-29 05:55:18 +00:00
parent dddded1414
commit a14736268b
1 changed files with 7 additions and 1 deletions
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8
plat/amd/versal2/plat_psci.c
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@ -21,6 +21,7 @@
#define PM_RET_ERROR_NOFEATURE U(19)
#define ALWAYSTRUE true
#define LINEAR_MODE BIT(1)
static uintptr_t _sec_entry;
@ -166,7 +167,12 @@ static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id,
switch (ioctl_id) {
case IOCTL_OSPI_MUX_SELECT:
mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1);
if ((arg1 == 0) || (arg1 == 1)) {
mmio_clrsetbits_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, LINEAR_MODE,
(arg1 ? LINEAR_MODE : 0));
} else {
ret = PM_RET_ERROR_ARGS;
}
break;
case IOCTL_UFS_TXRX_CFGRDY_GET:
ret = (int32_t) mmio_read_32(PMXC_IOU_SLCR_TX_RX_CONFIG_RDY);