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Merge changes from topic "xlnx_fix_plat_boolc_fn_ret" into integration

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* changes:
  fix(xilinx): avoid altering function parameters
  fix(versal-net): ignore the unused function return value
  fix(zynqmp): ignore the unused function return value
  fix(versal-net): modify conditions to have boolean type
  fix(versal): modify conditions to have boolean type
  fix(xilinx): modify conditions to have boolean type
  fix(zynqmp): modify conditions to have boolean type
This commit is contained in:
Joanna Farley 2024-11-01 14:29:20 +01:00 • committed by TrustedFirmware Code Review
commit dddded1414
16 changed files with 48 additions and 47 deletions
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8
plat/xilinx/common/ipi.c
View file

@ -144,11 +144,11 @@ int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
uint32_t status;
status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
if (status & IPI_BIT_MASK(remote)) {
if ((status & IPI_BIT_MASK(remote)) != 0U) {
ret |= IPI_MB_STATUS_SEND_PENDING;
}
status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
if (status & IPI_BIT_MASK(remote)) {
if ((status & IPI_BIT_MASK(remote)) != 0U) {
ret |= IPI_MB_STATUS_RECV_PENDING;
}
@ -170,11 +170,11 @@ void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking)
mmio_write_32(IPI_REG_BASE(local) + IPI_TRIG_OFFSET,
IPI_BIT_MASK(remote));
if (is_blocking) {
if (is_blocking != 0U) {
do {
status = mmio_read_32(IPI_REG_BASE(local) +
IPI_OBR_OFFSET);
} while (status & IPI_BIT_MASK(remote));
} while ((status & IPI_BIT_MASK(remote)) != 0U);
}
}

4
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
View file

@ -94,7 +94,7 @@ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
/* Validate IPI mailbox access */
ret = ipi_mb_validate(ipi_local_id, ipi_remote_id, is_secure);
if (ret)
if (ret != 0)
SMC_RET1(handle, ret);
switch (GET_SMC_NUM(smc_fid)) {
@ -128,7 +128,7 @@ uint64_t ipi_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
enable_interrupt = (x3 & IPI_SMC_ACK_EIRQ_MASK) ? 1 : 0;
ipi_mb_ack(ipi_local_id, ipi_remote_id);
if (enable_interrupt)
if (enable_interrupt != 0)
ipi_mb_enable_irq(ipi_local_id, ipi_remote_id);
SMC_RET1(handle, 0);
}

7
plat/xilinx/common/pm_service/pm_ipi.c
View file

@ -217,6 +217,7 @@ static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc,
enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count)
{
size_t i;
size_t local_count = count;
#if IPI_CRC_CHECK
uint32_t crc;
#endif
@ -225,8 +226,8 @@ enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count)
IPI_BUFFER_REQ_OFFSET;
enum pm_ret_status ret = PM_RET_SUCCESS;
if (count > IPI_BUFFER_MAX_WORDS) {
count = IPI_BUFFER_MAX_WORDS;
if (local_count > IPI_BUFFER_MAX_WORDS) {
local_count = IPI_BUFFER_MAX_WORDS;
}
for (i = 0; i < count; i++) {
@ -240,7 +241,7 @@ enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count)
/* Payload data is invalid as CRC validation failed
* Clear the payload to avoid leakage of data to upper layers
*/
memset(value, 0, count);
memset(value, 0, local_count);
}
#endif
return ret;

4
plat/xilinx/versal/plat_psci.c
View file

@ -146,7 +146,7 @@ static void __dead2 versal_system_off(void)
(void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope(), SECURE_FLAG);
while (1) {
while (true) {
wfi();
}
}
@ -185,7 +185,7 @@ static void __dead2 versal_system_reset(void)
(void)psci_cpu_off();
while (1) {
while (true) {
wfi();
}
}

2
plat/xilinx/versal/sip_svc_setup.c
View file

@ -80,7 +80,7 @@ uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4);
if (smc_fid & SIP_FID_MASK) {
if ((smc_fid & SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}

2
plat/xilinx/versal_net/bl31_versal_net_setup.c
View file

@ -214,7 +214,7 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
}
if (handler != NULL) {
handler(intr_id, flags, handle, cookie);
(void)handler(intr_id, flags, handle, cookie);
}
return 0;

12
plat/xilinx/versal_net/plat_psci_pm.c
View file

@ -42,7 +42,7 @@ static int32_t versal_net_pwr_domain_on(u_register_t mpidr)
return PSCI_E_INTERN_FAIL;
}
pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U,
(void)pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U,
versal_net_sec_entry >> 32, 0, 0);
/* Clear power down request */
@ -130,7 +130,7 @@ static void __dead2 versal_net_system_reset(void)
(void)psci_cpu_off();
while (1) {
while (true) {
wfi();
}
}
@ -166,7 +166,7 @@ static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMC to suspend this core */
pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry,
(void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry,
SECURE_FLAG);
/* TODO: disable coherency */
@ -223,10 +223,10 @@ static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *targe
static void __dead2 versal_net_system_off(void)
{
/* Send the power down request to the PMC */
pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
(void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope(), SECURE_FLAG);
while (1) {
while (true) {
wfi();
}
}
@ -257,7 +257,7 @@ static int32_t versal_net_validate_power_state(unsigned int power_state,
}
/* We expect the 'state id' to be zero */
if (psci_get_pstate_id(power_state)) {
if (psci_get_pstate_id(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}

2
plat/xilinx/versal_net/sip_svc_setup.c
View file

@ -69,7 +69,7 @@ static uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4);
if (smc_fid & SIP_FID_MASK) {
if ((smc_fid & SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}

16
plat/xilinx/zynqmp/plat_psci.c
View file

@ -58,7 +58,7 @@ static int32_t zynqmp_pwr_domain_on(u_register_t mpidr)
pm_client_wakeup(proc);
/* Send request to PMU to wake up selected APU CPU core */
pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING);
(void)pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING);
return PSCI_E_SUCCESS;
}
@ -88,7 +88,7 @@ static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state)
* invoking CPU_on function, during which resume address will
* be set.
*/
pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
(void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
}
static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
@ -109,7 +109,7 @@ static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state)
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMU to suspend this core */
pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry);
(void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry);
/* APU is to be turned off */
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
@ -166,10 +166,10 @@ static void __dead2 zynqmp_system_off(void)
plat_arm_interconnect_exit_coherency();
/* Send the power down request to the PMU */
pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN,
(void)pm_system_shutdown((uint32_t)PMF_SHUTDOWN_TYPE_SHUTDOWN,
pm_get_shutdown_scope());
while (1) {
while (true) {
wfi();
}
}
@ -180,10 +180,10 @@ static void __dead2 zynqmp_system_reset(void)
plat_arm_interconnect_exit_coherency();
/* Send the system reset request to the PMU */
pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
(void)pm_system_shutdown((uint32_t)PMF_SHUTDOWN_TYPE_RESET,
pm_get_shutdown_scope());
while (1) {
while (true) {
wfi();
}
}
@ -204,7 +204,7 @@ static int32_t zynqmp_validate_power_state(uint32_t power_state,
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
}
/* We expect the 'state id' to be zero */
if (psci_get_pstate_id(power_state)) {
if (psci_get_pstate_id(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
}

2
plat/xilinx/zynqmp/plat_zynqmp.c
View file

@ -10,7 +10,7 @@
int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
{
if (mpidr & MPIDR_CLUSTER_MASK) {
if ((mpidr & MPIDR_CLUSTER_MASK) != 0U) {
return -1;
}

16
plat/xilinx/zynqmp/pm_service/pm_api_clock.c
View file

@ -2456,14 +2456,14 @@ enum pm_ret_status pm_api_clock_get_num_clocks(uint32_t *nclocks)
void pm_api_clock_get_name(uint32_t clock_id, char *name)
{
if (clock_id == CLK_MAX) {
memcpy(name, END_OF_CLK, ((sizeof(END_OF_CLK) > CLK_NAME_LEN) ?
(void)memcpy(name, END_OF_CLK, ((sizeof(END_OF_CLK) > CLK_NAME_LEN) ?
CLK_NAME_LEN : sizeof(END_OF_CLK)));
} else if ((clock_id > CLK_MAX) || (!pm_clock_valid(clock_id))) {
memset(name, 0, CLK_NAME_LEN);
(void)memset(name, 0, CLK_NAME_LEN);
} else if (clock_id < CLK_MAX_OUTPUT_CLK) {
memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
(void)memcpy(name, clocks[clock_id].name, CLK_NAME_LEN);
} else {
memcpy(name, ext_clocks[clock_id - CLK_MAX_OUTPUT_CLK].name,
(void)memcpy(name, ext_clocks[clock_id - CLK_MAX_OUTPUT_CLK].name,
CLK_NAME_LEN);
}
}
@ -2499,7 +2499,7 @@ enum pm_ret_status pm_api_clock_get_topology(uint32_t clock_id,
return PM_RET_ERROR_NOTSUPPORTED;
}
memset(topology, 0, CLK_TOPOLOGY_PAYLOAD_LEN);
(void)memset(topology, 0, CLK_TOPOLOGY_PAYLOAD_LEN);
clock_nodes = *clocks[clock_id].nodes;
num_nodes = clocks[clock_id].num_nodes;
@ -2613,7 +2613,7 @@ enum pm_ret_status pm_api_clock_get_parents(uint32_t clock_id,
return PM_RET_ERROR_ARGS;
}
memset(parents, 0, CLK_PARENTS_PAYLOAD_LEN);
(void)memset(parents, 0, CLK_PARENTS_PAYLOAD_LEN);
/* Skip parent till index */
for (i = 0; i < index; i++) {
@ -2684,8 +2684,8 @@ enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id,
nodes = *clocks[clock_id].nodes;
for (i = 0; i < clocks[clock_id].num_nodes; i++) {
if (nodes[i].type == div_type) {
if (CLK_DIVIDER_POWER_OF_TWO &
nodes[i].typeflags) {
if ((CLK_DIVIDER_POWER_OF_TWO &
nodes[i].typeflags) != 0U) {
*max_div = (1U << (BIT(nodes[i].width) - 1U));
} else {
*max_div = BIT(nodes[i].width) - 1U;

2
plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
View file

@ -62,7 +62,7 @@ static enum pm_ret_status pm_ioctl_set_rpu_oper_mode(uint32_t mode)
{
uint32_t val;
if (mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) {
if ((mmio_read_32(CRL_APB_RST_LPD_TOP) & CRL_APB_RPU_AMBA_RESET) != 0U) {
return PM_RET_ERROR_ACCESS;
}

8
plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
View file

@ -2012,9 +2012,9 @@ enum pm_ret_status pm_api_pinctrl_get_num_func_groups(uint32_t fid,
void pm_api_pinctrl_get_function_name(uint32_t fid, char *name)
{
if (fid >= MAX_FUNCTION) {
memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
(void)memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
} else {
memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
(void)memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
}
}
@ -2049,7 +2049,7 @@ enum pm_ret_status pm_api_pinctrl_get_function_groups(uint32_t fid,
return PM_RET_ERROR_ARGS;
}
memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
(void)memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
grps = pinctrl_functions[fid].group_base;
end_of_grp_offset = grps + pinctrl_functions[fid].group_size;
@ -2094,7 +2094,7 @@ enum pm_ret_status pm_api_pinctrl_get_pin_groups(uint32_t pin,
return PM_RET_ERROR_ARGS;
}
memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
(void)memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN);
grps = *zynqmp_pin_groups[pin].groups;
if (grps == NULL) {

2
plat/xilinx/zynqmp/pm_service/pm_client.c
View file

@ -204,7 +204,7 @@ static void pm_client_set_wakeup_sources(void)
continue;
}
while (reg) {
while (reg != 0U) {
enum pm_node_id node;
uint32_t idx, ret, irq, lowest_set = reg & (-reg);

6
plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
View file

@ -1115,7 +1115,7 @@ static enum pm_ret_status pm_clock_gate(uint32_t clock_id,
return status;
}
if (enable) {
if (enable != 0U) {
api_id = PM_CLOCK_ENABLE;
} else {
api_id = PM_CLOCK_DISABLE;
@ -1297,7 +1297,7 @@ enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
return status;
}
if (pm_clock_has_div(clock_id, PM_CLOCK_DIV0_ID)) {
if ((pm_clock_has_div(clock_id, PM_CLOCK_DIV0_ID)) != 0U) {
/* Send request to the PMU to get div0 */
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
PM_CLOCK_DIV0_ID);
@ -1308,7 +1308,7 @@ enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
*divider = val;
}
if (pm_clock_has_div(clock_id, PM_CLOCK_DIV1_ID)) {
if ((pm_clock_has_div(clock_id, PM_CLOCK_DIV1_ID)) != 0U) {
/* Send request to the PMU to get div1 */
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
PM_CLOCK_DIV1_ID);

2
plat/xilinx/zynqmp/sip_svc_setup.c
View file

@ -81,7 +81,7 @@ static uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
smc_fid, x1, x2, x3, x4);
if (smc_fid & SIP_FID_MASK) {
if ((smc_fid & (uint32_t)SIP_FID_MASK) != 0U) {
WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}