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Merge "feat(plat/tc): enable MPAM functionality of L3 DSU cache" into integration

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Manish V Badarkhe 2023-01-27 12:50:27 +01:00 • committed by TrustedFirmware Code Review
commit 9dea6fa680
1 changed files with 10 additions and 1 deletions
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11
fdts/tc.dts
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -519,6 +519,15 @@
};
};
/*
* L3 cache in the DSU is the Memory System Component (MSC)
* The MPAM registers are accessed through utility bus in the DSU
*/
msc0 {
compatible = "arm,mpam-msc";
reg = <0x1 0x00010000 0x0 0x2000>;
};
ete0 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU0>;